1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2004 Freescale Semiconductor. 4 * Jeff Brown 5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 6 * 7 * (C) Copyright 2000-2002 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 */ 10 11 #include <common.h> 12 #include <clock_legacy.h> 13 #include <mpc86xx.h> 14 #include <asm/global_data.h> 15 #include <asm/processor.h> 16 #include <asm/io.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* used in some defintiions of CONFIG_SYS_CLK_FREQ */ 21 extern unsigned long get_board_sys_clk(unsigned long dummy); 22 get_sys_info(sys_info_t * sys_info)23void get_sys_info(sys_info_t *sys_info) 24 { 25 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 26 volatile ccsr_gur_t *gur = &immap->im_gur; 27 uint plat_ratio, e600_ratio; 28 29 plat_ratio = (gur->porpllsr) & 0x0000003e; 30 plat_ratio >>= 1; 31 32 switch (plat_ratio) { 33 case 0x0: 34 sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; 35 break; 36 case 0x02: 37 case 0x03: 38 case 0x04: 39 case 0x05: 40 case 0x06: 41 case 0x08: 42 case 0x09: 43 case 0x0a: 44 case 0x0c: 45 case 0x10: 46 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 47 break; 48 default: 49 sys_info->freq_systembus = 0; 50 break; 51 } 52 53 e600_ratio = (gur->porpllsr) & 0x003f0000; 54 e600_ratio >>= 16; 55 56 switch (e600_ratio) { 57 case 0x10: 58 sys_info->freq_processor = 2 * sys_info->freq_systembus; 59 break; 60 case 0x19: 61 sys_info->freq_processor = 5 * sys_info->freq_systembus / 2; 62 break; 63 case 0x20: 64 sys_info->freq_processor = 3 * sys_info->freq_systembus; 65 break; 66 case 0x39: 67 sys_info->freq_processor = 7 * sys_info->freq_systembus / 2; 68 break; 69 case 0x28: 70 sys_info->freq_processor = 4 * sys_info->freq_systembus; 71 break; 72 case 0x1d: 73 sys_info->freq_processor = 9 * sys_info->freq_systembus / 2; 74 break; 75 default: 76 sys_info->freq_processor = e600_ratio + 77 sys_info->freq_systembus; 78 break; 79 } 80 81 sys_info->freq_localbus = sys_info->freq_systembus; 82 } 83 84 85 /* 86 * Measure CPU clock speed (core clock GCLK1, GCLK2) 87 * (Approx. GCLK frequency in Hz) 88 */ 89 get_clocks(void)90int get_clocks(void) 91 { 92 sys_info_t sys_info; 93 94 get_sys_info(&sys_info); 95 gd->cpu_clk = sys_info.freq_processor; 96 gd->bus_clk = sys_info.freq_systembus; 97 gd->arch.lbc_clk = sys_info.freq_localbus; 98 99 /* 100 * The base clock for I2C depends on the actual SOC. Unfortunately, 101 * there is no pattern that can be used to determine the frequency, so 102 * the only choice is to look up the actual SOC number and use the value 103 * for that SOC. This information is taken from application note 104 * AN2919. 105 */ 106 #ifdef CONFIG_ARCH_MPC8610 107 gd->arch.i2c1_clk = sys_info.freq_systembus; 108 #else 109 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 110 #endif 111 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 112 113 if (gd->cpu_clk != 0) 114 return 0; 115 else 116 return 1; 117 } 118 119 120 /* 121 * get_bus_freq 122 * Return system bus freq in Hz 123 */ 124 get_bus_freq(ulong dummy)125ulong get_bus_freq(ulong dummy) 126 { 127 ulong val; 128 sys_info_t sys_info; 129 130 get_sys_info(&sys_info); 131 val = sys_info.freq_systembus; 132 133 return val; 134 } 135