1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Hitachi Power Grids KMETER1 Device Tree Source 4 * 5 * 2008-2011 DENX Software Engineering GmbH 6 * Copyright (C) 2020 Heiko Schocher <hs@denx.de> 7 */ 8 9/dts-v1/; 10 11#include "km836x.dtsi" 12 13/ { 14 model = "KMETER1"; 15 compatible = "keymile,KMETER1"; 16 17 aliases { 18 ethernet0 = &enet_piggy2; 19 ethernet1 = &enet_estar1; 20 ethernet2 = &enet_estar2; 21 ethernet3 = &enet_eth1; 22 ethernet4 = &enet_eth2; 23 ethernet5 = &enet_eth3; 24 ethernet6 = &enet_eth4; 25 serial0 = &serial0; 26 }; 27}; 28 29&i2c0 { 30 mux@70 { 31 compatible = "nxp,pca9547"; 32 reg = <0x70>; 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 i2c@1 { 37 reg = <1>; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 /* Inventory EEPROM of the unit itself */ 42 ivm@50 { 43 label = "MAIN_CTRL"; 44 compatible = "dummy"; 45 reg = <0x50>; 46 }; 47 }; 48 49 i2c@2 { 50 reg = <2>; 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 /* Temperature sensors */ 55 temp@48 { 56 label = "Top"; 57 compatible = "national,lm75"; 58 reg = <0x48>; 59 }; 60 61 temp@49 { 62 label = "Control"; 63 compatible = "national,lm75"; 64 reg = <0x49>; 65 }; 66 67 temp@4a { 68 label = "Power"; 69 compatible = "national,lm75"; 70 reg = <0x4a>; 71 }; 72 73 temp@4b { 74 label = "Front"; 75 compatible = "national,lm75"; 76 reg = <0x4b>; 77 }; 78 }; 79 }; 80}; 81 82&serial0 { 83 status = "okay"; 84}; 85 86&par_io { 87 pio_ucc1: ucc_pin@0 { 88 pio-map = < 89 /* port pin dir open_drain assignment has_irq */ 90 0 1 3 0 2 0 /* MDIO */ 91 0 2 1 0 1 0 /* MDC */ 92 93 0 3 1 0 1 0 /* TxD0 */ 94 0 4 1 0 1 0 /* TxD1 */ 95 0 5 1 0 1 0 /* TxD2 */ 96 0 6 1 0 1 0 /* TxD3 */ 97 0 9 2 0 1 0 /* RxD0 */ 98 0 10 2 0 1 0 /* RxD1 */ 99 0 11 2 0 1 0 /* RxD2 */ 100 0 12 2 0 1 0 /* RxD3 */ 101 0 7 1 0 1 0 /* TX_EN */ 102 0 8 1 0 1 0 /* TX_ER */ 103 0 15 2 0 1 0 /* RX_DV */ 104 0 16 2 0 1 0 /* RX_ER */ 105 0 0 2 0 1 0 /* RX_CLK */ 106 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 107 2 8 2 0 1 0 /* GTX125 - CLK9 */ 108 >; 109 }; 110 111 pio_ucc2: ucc_pin@1 { 112 pio-map = < 113 /* port pin dir open_drain assignment has_irq */ 114 0 1 3 0 2 0 /* MDIO */ 115 0 2 1 0 1 0 /* MDC */ 116 117 0 17 1 0 1 0 /* TxD0 */ 118 0 18 1 0 1 0 /* TxD1 */ 119 0 19 1 0 1 0 /* TxD2 */ 120 0 20 1 0 1 0 /* TxD3 */ 121 0 23 2 0 1 0 /* RxD0 */ 122 0 24 2 0 1 0 /* RxD1 */ 123 0 25 2 0 1 0 /* RxD2 */ 124 0 26 2 0 1 0 /* RxD3 */ 125 0 21 1 0 1 0 /* TX_EN */ 126 0 22 1 0 1 0 /* TX_ER */ 127 0 29 2 0 1 0 /* RX_DV */ 128 0 30 2 0 1 0 /* RX_ER */ 129 0 31 2 0 1 0 /* RX_CLK */ 130 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ 131 2 3 2 0 1 0 /* GTX125 - CLK4 */ 132 >; 133 }; 134 135 pio_ucc4: ucc_pin@3 { 136 pio-map = < 137 /* port pin dir open_drain assignment has_irq */ 138 0 1 3 0 2 0 /* MDIO */ 139 0 2 1 0 1 0 /* MDC */ 140 141 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 142 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 143 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 144 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 145 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 146 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 147 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 148 149 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ 150 >; 151 }; 152 153 pio_ucc5: ucc_pin@4 { 154 pio-map = < 155 /* port pin dir open_drain assignment has_irq */ 156 0 1 3 0 2 0 /* MDIO */ 157 0 2 1 0 1 0 /* MDC */ 158 159 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 160 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 161 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 162 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 163 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 164 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 165 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ 166 >; 167 }; 168 169 pio_ucc6: ucc_pin@5 { 170 pio-map = < 171 /* port pin dir open_drain assignment has_irq */ 172 0 1 3 0 2 0 /* MDIO */ 173 0 2 1 0 1 0 /* MDC */ 174 175 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ 176 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ 177 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ 178 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ 179 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ 180 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 181 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ 182 >; 183 }; 184 185 pio_ucc7: ucc_pin@6 { 186 pio-map = < 187 /* port pin dir open_drain assignment has_irq */ 188 0 1 3 0 2 0 /* MDIO */ 189 0 2 1 0 1 0 /* MDC */ 190 191 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ 192 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ 193 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ 194 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ 195 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ 196 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 197 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ 198 >; 199 }; 200 201 pio_ucc8: ucc_pin@7 { 202 pio-map = < 203 /* port pin dir open_drain assignment has_irq */ 204 0 1 3 0 2 0 /* MDIO */ 205 0 2 1 0 1 0 /* MDC */ 206 207 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ 208 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ 209 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ 210 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ 211 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ 212 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ 213 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ 214 215 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ 216 >; 217 }; 218 219 pio_spi: spi_pin@01 { 220 pio-map = < 221 /* port pin dir open_drain assignment has_irq */ 222 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */ 223 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */ 224 >; 225 }; 226 227 /* UCC3 as HDLC controller for ICN */ 228 pio5: ucc_pin@02 { 229 pio-map = < 230 /* port pin dir open_drain assignment has_irq */ 231 1 0 1 0 1 0 /* TxD0 */ 232 1 6 2 0 1 0 /* RxD0 */ 233 1 12 2 0 1 0 /* CTS */ 234 2 11 2 0 1 0 /* TX-CLK12 */ 235 >; 236 }; 237 238 pio_tdm: tdm_pin@00 { 239 pio-map = < 240 /* port pin dir open_drain assignment has_irq */ 241 /* TDMa */ 242 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ 243 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ 244 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ 245 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ 246 /* TDMb */ 247 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ 248 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ 249 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ 250 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ 251 /* TDMc */ 252 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ 253 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ 254 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ 255 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ 256 /* TDMd */ 257 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ 258 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ 259 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ 260 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ 261 /* TDMe */ 262 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ 263 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ 264 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ 265 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ 266 /* TDMf */ 267 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ 268 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ 269 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ 270 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ 271 /* TDMg */ 272 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ 273 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ 274 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ 275 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ 276 /* TDMh */ 277 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ 278 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ 279 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ 280 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ 281 /* RxTxClk0/1 */ 282 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ 283 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ 284 /* RxTxSync0/1 */ 285 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ 286 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ 287 }; 288}; 289 290&qe { 291 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 292 enet_estar1: ucc@2000 { 293 device_type = "network"; 294 compatible = "ucc_geth"; 295 cell-index = <1>; 296 reg = <0x2000 0x200>; 297 interrupts = <32>; 298 interrupt-parent = <&qeic>; 299 local-mac-address = [ 00 00 00 00 00 00 ]; 300 rx-clock-name = "none"; 301 tx-clock-name = "clk9"; 302 phy-handle = <&phy_estar1>; 303 phy-connection-type = "rgmii-id"; 304 pio-handle = <&pio_ucc1>; 305 }; 306 307 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 308 enet_estar2: ucc@3000 { 309 device_type = "network"; 310 compatible = "ucc_geth"; 311 cell-index = <2>; 312 reg = <0x3000 0x200>; 313 interrupts = <33>; 314 interrupt-parent = <&qeic>; 315 local-mac-address = [ 00 00 00 00 00 00 ]; 316 rx-clock-name = "none"; 317 tx-clock-name = "clk4"; 318 phy-handle = <&phy_estar2>; 319 phy-connection-type = "rgmii-id"; 320 pio-handle = <&pio_ucc2>; 321 }; 322 323 /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 324 enet_piggy2: ucc@3200 { 325 device_type = "network"; 326 compatible = "ucc_geth"; 327 cell-index = <4>; 328 reg = <0x3200 0x200>; 329 interrupts = <35>; 330 interrupt-parent = <&qeic>; 331 local-mac-address = [ 00 00 00 00 00 00 ]; 332 rx-clock-name = "none"; 333 tx-clock-name = "clk17"; 334 phy-handle = <&phy_piggy2>; 335 phy-connection-type = "rmii"; 336 pio-handle = <&pio_ucc4>; 337 }; 338 339 /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 340 enet_eth1: ucc@2400 { 341 device_type = "network"; 342 compatible = "ucc_geth"; 343 cell-index = <5>; 344 reg = <0x2400 0x200>; 345 interrupts = <40>; 346 interrupt-parent = <&qeic>; 347 local-mac-address = [ 00 00 00 00 00 00 ]; 348 rx-clock-name = "none"; 349 tx-clock-name = "clk16"; 350 phy-handle = <&phy_eth1>; 351 phy-connection-type = "rmii"; 352 pio-handle = <&pio_ucc5>; 353 }; 354 355 /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 356 enet_eth2: ucc@3400 { 357 device_type = "network"; 358 compatible = "ucc_geth"; 359 cell-index = <6>; 360 reg = <0x3400 0x200>; 361 interrupts = <41>; 362 interrupt-parent = <&qeic>; 363 local-mac-address = [ 00 00 00 00 00 00 ]; 364 rx-clock-name = "none"; 365 tx-clock-name = "clk16"; 366 phy-handle = <&phy_eth2>; 367 phy-connection-type = "rmii"; 368 pio-handle = <&pio_ucc6>; 369 }; 370 371 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 372 enet_eth3: ucc@2600 { 373 device_type = "network"; 374 compatible = "ucc_geth"; 375 cell-index = <7>; 376 reg = <0x2600 0x200>; 377 interrupts = <42>; 378 interrupt-parent = <&qeic>; 379 local-mac-address = [ 00 00 00 00 00 00 ]; 380 rx-clock-name = "none"; 381 tx-clock-name = "clk16"; 382 phy-handle = <&phy_eth3>; 383 phy-connection-type = "rmii"; 384 pio-handle = <&pio_ucc7>; 385 }; 386 387 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 388 enet_eth4: ucc@3600 { 389 device_type = "network"; 390 compatible = "ucc_geth"; 391 cell-index = <8>; 392 reg = <0x3600 0x200>; 393 interrupts = <43>; 394 interrupt-parent = <&qeic>; 395 local-mac-address = [ 00 00 00 00 00 00 ]; 396 rx-clock-name = "none"; 397 tx-clock-name = "clk16"; 398 phy-handle = <&phy_eth4>; 399 phy-connection-type = "rmii"; 400 pio-handle = <&pio_ucc8>; 401 }; 402 403 mdio@3320 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x3320 0x18>; 407 compatible = "fsl,ucc-mdio"; 408 409 /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 410 phy_piggy2: ethernet-phy@0 { 411 reg = <0x0>; 412 }; 413 414 /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 415 phy_eth1: ethernet-phy@8 { 416 reg = <0x08>; 417 }; 418 419 /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 420 phy_eth2: ethernet-phy@9 { 421 reg = <0x09>; 422 }; 423 424 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 425 phy_eth3: ethernet-phy@a { 426 reg = <0x0a>; 427 }; 428 429 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 430 phy_eth4: ethernet-phy@b { 431 reg = <0x0b>; 432 }; 433 434 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 435 phy_estar1: ethernet-phy@10 { 436 interrupt-parent = <&ipic>; 437 interrupts = <17 0x8>; 438 reg = <0x10>; 439 }; 440 441 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 442 phy_estar2: ethernet-phy@11 { 443 interrupt-parent = <&ipic>; 444 interrupts = <18 0x8>; 445 reg = <0x11>; 446 }; 447 }; 448}; 449 450&localbus { 451 ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ 452 1 0 0xe8000000 0x01000000 /* LB 1 */ 453 3 0 0xa0000000 0x10000000>; /* LB 3 */ 454 455 flash@0,0 { 456 compatible = "cfi-flash"; 457 reg = <0 0 0x04000000>; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 bank-width = <2>; 461 partition@0 { /* 768KB */ 462 label = "u-boot"; 463 reg = <0 0xC0000>; 464 }; 465 partition@c0000 { /* 128KB */ 466 label = "env"; 467 reg = <0xC0000 0x20000>; 468 }; 469 partition@e0000 { /* 128KB */ 470 label = "envred"; 471 reg = <0xE0000 0x20000>; 472 }; 473 partition@100000 { /* 64512KB */ 474 label = "ubi0"; 475 reg = <0x100000 0x3F00000>; 476 }; 477 }; 478}; 479 480#include "kmeter1-uboot.dtsi" 481