1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2013-2014 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/include/ "e5500_power_isa.dtsi"
11
12/ {
13	#address-cells = <2>;
14	#size-cells = <2>;
15	interrupt-parent = <&mpic>;
16
17	aliases {
18		ccsr = &soc;
19		dcsr = &dcsr;
20
21		serial0 = &serial0;
22		serial1 = &serial1;
23		serial2 = &serial2;
24		serial3 = &serial3;
25		pci0 = &pci0;
26		pci1 = &pci1;
27		pci2 = &pci2;
28		pci3 = &pci3;
29		usb0 = &usb0;
30		usb1 = &usb1;
31		sdhc = &sdhc;
32
33		crypto = &crypto;
34
35		fman0 = &fman0;
36		ethernet0 = &enet0;
37		ethernet1 = &enet1;
38		ethernet2 = &enet2;
39		ethernet3 = &enet3;
40		ethernet4 = &enet4;
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		cpu0: PowerPC,e5500@0 {
48			device_type = "cpu";
49			reg = <0>;
50			clocks = <&clockgen 1 0>;
51			next-level-cache = <&L2_1>;
52			#cooling-cells = <2>;
53			L2_1: l2-cache {
54				next-level-cache = <&cpc>;
55			};
56		};
57		cpu1: PowerPC,e5500@1 {
58			device_type = "cpu";
59			reg = <1>;
60			clocks = <&clockgen 1 1>;
61			next-level-cache = <&L2_2>;
62			#cooling-cells = <2>;
63			L2_2: l2-cache {
64				next-level-cache = <&cpc>;
65			};
66		};
67		cpu2: PowerPC,e5500@2 {
68			device_type = "cpu";
69			reg = <2>;
70			clocks = <&clockgen 1 2>;
71			next-level-cache = <&L2_3>;
72			#cooling-cells = <2>;
73			L2_3: l2-cache {
74				next-level-cache = <&cpc>;
75			};
76		};
77		cpu3: PowerPC,e5500@3 {
78			device_type = "cpu";
79			reg = <3>;
80			clocks = <&clockgen 1 3>;
81			next-level-cache = <&L2_4>;
82			#cooling-cells = <2>;
83			L2_4: l2-cache {
84				next-level-cache = <&cpc>;
85			};
86		};
87	};
88};
89