1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 Google LLC
4 */
5
6 #define LOG_CATEGORY LOGC_BOOT
7
8 #include <common.h>
9 #include <binman_sym.h>
10 #include <bootstage.h>
11 #include <dm.h>
12 #include <image.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <spi.h>
16 #include <spl.h>
17 #include <spi_flash.h>
18 #include <asm/fast_spi.h>
19 #include <asm/spl.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/iomap.h>
22 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
24
25 /* This reads the next phase from mapped SPI flash */
rom_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)26 static int rom_load_image(struct spl_image_info *spl_image,
27 struct spl_boot_device *bootdev)
28 {
29 ulong spl_pos = spl_get_image_pos();
30 ulong spl_size = spl_get_image_size();
31 struct udevice *dev;
32 ulong map_base;
33 size_t map_size;
34 uint offset;
35 int ret;
36
37 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
38 spl_image->entry_point = spl_get_image_text_base();
39 spl_image->load_addr = spl_image->entry_point;
40 spl_image->os = IH_OS_U_BOOT;
41 spl_image->name = "U-Boot";
42 log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size);
43
44 if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
45 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
46 if (ret)
47 return log_msg_ret("spi_flash", ret);
48 if (!dev)
49 return log_msg_ret("spi_flash dev", -ENODEV);
50 ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
51 if (ret)
52 return log_msg_ret("mmap", ret);
53 } else {
54 ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
55 &offset);
56 if (ret)
57 return ret;
58 }
59 spl_pos += map_base & ~0xff000000;
60 log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos,
61 spl_image->load_addr);
62 bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
63 memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
64 cpu_flush_l1d_to_l2();
65 bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
66
67 return 0;
68 }
69 SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
70
71 #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
72
apl_flash_std_read(struct udevice * dev,u32 offset,size_t len,void * buf)73 static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
74 void *buf)
75 {
76 struct spi_flash *flash = dev_get_uclass_priv(dev);
77 struct mtd_info *mtd = &flash->mtd;
78 size_t retlen;
79
80 return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
81 }
82
apl_flash_probe(struct udevice * dev)83 static int apl_flash_probe(struct udevice *dev)
84 {
85 return spi_flash_std_probe(dev);
86 }
87
88 static const struct dm_spi_flash_ops apl_flash_ops = {
89 .read = apl_flash_std_read,
90 };
91
92 static const struct udevice_id apl_flash_ids[] = {
93 { .compatible = "jedec,spi-nor" },
94 { }
95 };
96
97 U_BOOT_DRIVER(winbond_w25q128fw) = {
98 .name = "winbond_w25q128fw",
99 .id = UCLASS_SPI_FLASH,
100 .of_match = apl_flash_ids,
101 .probe = apl_flash_probe,
102 .priv_auto = sizeof(struct spi_nor),
103 .ops = &apl_flash_ops,
104 };
105
106 /* This uses a SPI flash device to read the next phase */
spl_fast_spi_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)107 static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
108 struct spl_boot_device *bootdev)
109 {
110 ulong spl_pos = spl_get_image_pos();
111 ulong spl_size = spl_get_image_size();
112 struct udevice *dev;
113 int ret;
114
115 ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
116 if (ret)
117 return ret;
118
119 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
120 spl_image->entry_point = spl_phase() == PHASE_TPL ?
121 CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
122 spl_image->load_addr = spl_image->entry_point;
123 spl_image->os = IH_OS_U_BOOT;
124 spl_image->name = "U-Boot";
125 spl_pos &= ~0xff000000;
126 log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
127 ret = spi_flash_read_dm(dev, spl_pos, spl_size,
128 (void *)spl_image->load_addr);
129 cpu_flush_l1d_to_l2();
130 if (ret)
131 return ret;
132
133 return 0;
134 }
135 SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
136 spl_fast_spi_load_image);
137
board_boot_order(u32 * spl_boot_list)138 void board_boot_order(u32 *spl_boot_list)
139 {
140 bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
141
142 if (use_spi_flash) {
143 spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
144 spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
145 } else {
146 spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
147 spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
148 }
149 }
150
151 #else
152
board_boot_order(u32 * spl_boot_list)153 void board_boot_order(u32 *spl_boot_list)
154 {
155 spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
156 }
157 #endif
158