1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 Google, Inc
4 *
5 * Based on code from coreboot src/soc/intel/broadwell/me_status.c
6 */
7
8 #include <common.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <asm/arch/me.h>
12 #include <linux/delay.h>
13
me_read_dword_ptr(struct udevice * dev,void * ptr,int offset)14 static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
15 {
16 u32 dword;
17
18 dm_pci_read_config32(dev, offset, &dword);
19 memcpy(ptr, &dword, sizeof(dword));
20 }
21
intel_me_hsio_version(struct udevice * dev,uint16_t * versionp,uint16_t * checksump)22 int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
23 uint16_t *checksump)
24 {
25 int count;
26 u32 hsiover;
27 struct me_hfs hfs;
28
29 /* Query for HSIO version, overloads H_GS and HFS */
30 dm_pci_write_config32(dev, PCI_ME_H_GS,
31 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
32
33 /* Must wait for ME acknowledgement */
34 for (count = ME_RETRY; count > 0; --count) {
35 me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
36 if (hfs.bios_msg_ack)
37 break;
38 udelay(ME_DELAY);
39 }
40 if (!count) {
41 debug("ERROR: ME failed to respond\n");
42 return -ETIMEDOUT;
43 }
44
45 /* HSIO version should be in HFS_5 */
46 dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
47 *versionp = hsiover >> 16;
48 *checksump = hsiover & 0xffff;
49
50 debug("ME: HSIO Version : %d (CRC 0x%04x)\n",
51 *versionp, *checksump);
52
53 /* Reset registers to normal behavior */
54 dm_pci_write_config32(dev, PCI_ME_H_GS,
55 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
56
57 return 0;
58 }
59