1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From coreboot southbridge/intel/bd82x6x/lpc.c
4 *
5 * Copyright (C) 2008-2009 coresystems GmbH
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <fdtdec.h>
12 #include <log.h>
13 #include <rtc.h>
14 #include <pci.h>
15 #include <asm/global_data.h>
16 #include <asm/intel_regs.h>
17 #include <asm/interrupt.h>
18 #include <asm/io.h>
19 #include <asm/ioapic.h>
20 #include <asm/lpc_common.h>
21 #include <asm/pci.h>
22 #include <asm/arch/pch.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define NMI_OFF 0
27
28 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
29 #define TEST_SMM_FLASH_LOCKDOWN 0
30
pch_enable_apic(struct udevice * pch)31 static int pch_enable_apic(struct udevice *pch)
32 {
33 u32 reg32;
34 int i;
35
36 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
37 dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
38
39 writel(0, IO_APIC_INDEX);
40 writel(1 << 25, IO_APIC_DATA);
41
42 /* affirm full set of redirection table entries ("write once") */
43 writel(1, IO_APIC_INDEX);
44 reg32 = readl(IO_APIC_DATA);
45 writel(1, IO_APIC_INDEX);
46 writel(reg32, IO_APIC_DATA);
47
48 writel(0, IO_APIC_INDEX);
49 reg32 = readl(IO_APIC_DATA);
50 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
51 if (reg32 != (1 << 25)) {
52 printf("APIC Error - cannot write to registers\n");
53 return -EPERM;
54 }
55
56 debug("Dumping IOAPIC registers\n");
57 for (i = 0; i < 3; i++) {
58 writel(i, IO_APIC_INDEX);
59 debug(" reg 0x%04x:", i);
60 reg32 = readl(IO_APIC_DATA);
61 debug(" 0x%08x\n", reg32);
62 }
63
64 /* Select Boot Configuration register. */
65 writel(3, IO_APIC_INDEX);
66
67 /* Use Processor System Bus to deliver interrupts. */
68 writel(1, IO_APIC_DATA);
69
70 return 0;
71 }
72
pch_enable_serial_irqs(struct udevice * pch)73 static void pch_enable_serial_irqs(struct udevice *pch)
74 {
75 u32 value;
76
77 /* Set packet length and toggle silent mode bit for one frame. */
78 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
79 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
80 dm_pci_write_config8(pch, SERIRQ_CNTL, value);
81 #else
82 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
83 #endif
84 }
85
pch_pirq_init(struct udevice * pch)86 static int pch_pirq_init(struct udevice *pch)
87 {
88 uint8_t route[8], *ptr;
89
90 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
91 "intel,pirq-routing", route, sizeof(route)))
92 return -EINVAL;
93 ptr = route;
94 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
95 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
96 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
97 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
98
99 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
100 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
101 dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
102 dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
103
104 /*
105 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
106 * here. It's unclear if it is needed
107 */
108 return 0;
109 }
110
pch_gpi_routing(struct udevice * pch)111 static int pch_gpi_routing(struct udevice *pch)
112 {
113 u8 route[16];
114 u32 reg;
115 int gpi;
116
117 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
118 "intel,gpi-routing", route, sizeof(route)))
119 return -EINVAL;
120
121 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
122 reg |= route[gpi] << (gpi * 2);
123
124 dm_pci_write_config32(pch, 0xb8, reg);
125
126 return 0;
127 }
128
pch_power_options(struct udevice * pch)129 static int pch_power_options(struct udevice *pch)
130 {
131 const void *blob = gd->fdt_blob;
132 int node = dev_of_offset(pch);
133 u8 reg8;
134 u16 reg16, pmbase;
135 u32 reg32;
136 const char *state;
137 int pwr_on;
138 int nmi_option;
139 int ret;
140
141 /*
142 * Which state do we want to goto after g3 (power restored)?
143 * 0 == S0 Full On
144 * 1 == S5 Soft Off
145 *
146 * If the option is not existent (Laptops), use Kconfig setting.
147 * TODO(sjg@chromium.org): Make this configurable
148 */
149 pwr_on = MAINBOARD_POWER_ON;
150
151 dm_pci_read_config16(pch, GEN_PMCON_3, ®16);
152 reg16 &= 0xfffe;
153 switch (pwr_on) {
154 case MAINBOARD_POWER_OFF:
155 reg16 |= 1;
156 state = "off";
157 break;
158 case MAINBOARD_POWER_ON:
159 reg16 &= ~1;
160 state = "on";
161 break;
162 case MAINBOARD_POWER_KEEP:
163 reg16 &= ~1;
164 state = "state keep";
165 break;
166 default:
167 state = "undefined";
168 }
169
170 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
171 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
172
173 reg16 &= ~(1 << 10);
174 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
175
176 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
177
178 dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
179 debug("Set power %s after power failure.\n", state);
180
181 /* Set up NMI on errors. */
182 reg8 = inb(0x61);
183 reg8 &= 0x0f; /* Higher Nibble must be 0 */
184 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
185 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
186 outb(reg8, 0x61);
187
188 reg8 = inb(0x70);
189 /* TODO(sjg@chromium.org): Make this configurable */
190 nmi_option = NMI_OFF;
191 if (nmi_option) {
192 debug("NMI sources enabled.\n");
193 reg8 &= ~(1 << 7); /* Set NMI. */
194 } else {
195 debug("NMI sources disabled.\n");
196 /* Can't mask NMI from PCI-E and NMI_NOW */
197 reg8 |= (1 << 7);
198 }
199 outb(reg8, 0x70);
200
201 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
202 dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
203 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
204 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
205 #if DEBUG_PERIODIC_SMIS
206 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
207 reg16 |= (3 << 0); /* Periodic SMI every 8s */
208 #endif
209 dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
210
211 /* Set the board's GPI routing. */
212 ret = pch_gpi_routing(pch);
213 if (ret)
214 return ret;
215
216 dm_pci_read_config16(pch, 0x40, &pmbase);
217 pmbase &= 0xfffe;
218
219 writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
220 (ulong)pmbase + GPE0_EN);
221 writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
222 (ulong)pmbase + ALT_GP_SMI_EN);
223
224 /* Set up power management block and determine sleep mode */
225 reg32 = inl(pmbase + 0x04); /* PM1_CNT */
226 reg32 &= ~(7 << 10); /* SLP_TYP */
227 reg32 |= (1 << 0); /* SCI_EN */
228 outl(reg32, pmbase + 0x04);
229
230 /* Clear magic status bits to prevent unexpected wake */
231 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
232 clrbits_le32(RCB_REG(0x3f02), 0xf);
233
234 return 0;
235 }
236
pch_rtc_init(struct udevice * pch)237 static void pch_rtc_init(struct udevice *pch)
238 {
239 int rtc_failed;
240 u8 reg8;
241
242 dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
243 rtc_failed = reg8 & RTC_BATTERY_DEAD;
244 if (rtc_failed) {
245 reg8 &= ~RTC_BATTERY_DEAD;
246 dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
247 }
248 debug("rtc_failed = 0x%x\n", rtc_failed);
249
250 /* TODO: Handle power failure */
251 if (rtc_failed)
252 printf("RTC power failed\n");
253 }
254
255 /* CougarPoint PCH Power Management init */
cpt_pm_init(struct udevice * pch)256 static void cpt_pm_init(struct udevice *pch)
257 {
258 debug("CougarPoint PM init\n");
259 dm_pci_write_config8(pch, 0xa9, 0x47);
260 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
261
262 setbits_le32(RCB_REG(0x228c), 1 << 0);
263 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
264 setbits_le32(RCB_REG(0x0900), 1 << 14);
265 writel(0xc0388400, RCB_REG(0x2304));
266 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
267 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
268 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
269 writel(0x050f0000, RCB_REG(0x3318));
270 writel(0x04000000, RCB_REG(0x3324));
271 setbits_le32(RCB_REG(0x3340), 0xfffff);
272 setbits_le32(RCB_REG(0x3344), 1 << 1);
273
274 writel(0x0001c000, RCB_REG(0x3360));
275 writel(0x00061100, RCB_REG(0x3368));
276 writel(0x7f8fdfff, RCB_REG(0x3378));
277 writel(0x000003fc, RCB_REG(0x337c));
278 writel(0x00001000, RCB_REG(0x3388));
279 writel(0x0001c000, RCB_REG(0x3390));
280 writel(0x00000800, RCB_REG(0x33a0));
281 writel(0x00001000, RCB_REG(0x33b0));
282 writel(0x00093900, RCB_REG(0x33c0));
283 writel(0x24653002, RCB_REG(0x33cc));
284 writel(0x062108fe, RCB_REG(0x33d0));
285 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
286 writel(0x01010000, RCB_REG(0x3a28));
287 writel(0x01010404, RCB_REG(0x3a2c));
288 writel(0x01041041, RCB_REG(0x3a80));
289 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
290 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
291 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
292 writel(0x00000001, RCB_REG(0x3a6c));
293 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
294 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
295 writel(0, RCB_REG(0x33c8));
296 setbits_le32(RCB_REG(0x21b0), 0xf);
297 }
298
299 /* PantherPoint PCH Power Management init */
ppt_pm_init(struct udevice * pch)300 static void ppt_pm_init(struct udevice *pch)
301 {
302 debug("PantherPoint PM init\n");
303 dm_pci_write_config8(pch, 0xa9, 0x47);
304 setbits_le32(RCB_REG(0x2238), 1 << 0);
305 setbits_le32(RCB_REG(0x228c), 1 << 0);
306 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
307 setbits_le16(RCB_REG(0x0900), 1 << 14);
308 writel(0xc03b8400, RCB_REG(0x2304));
309 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
310 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
311 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
312 writel(0x054f0000, RCB_REG(0x3318));
313 writel(0x04000000, RCB_REG(0x3324));
314 setbits_le32(RCB_REG(0x3340), 0xfffff);
315 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
316 writel(0x0001c000, RCB_REG(0x3360));
317 writel(0x00061100, RCB_REG(0x3368));
318 writel(0x7f8fdfff, RCB_REG(0x3378));
319 writel(0x000003fd, RCB_REG(0x337c));
320 writel(0x00001000, RCB_REG(0x3388));
321 writel(0x0001c000, RCB_REG(0x3390));
322 writel(0x00000800, RCB_REG(0x33a0));
323 writel(0x00001000, RCB_REG(0x33b0));
324 writel(0x00093900, RCB_REG(0x33c0));
325 writel(0x24653002, RCB_REG(0x33cc));
326 writel(0x067388fe, RCB_REG(0x33d0));
327 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
328 writel(0x01010000, RCB_REG(0x3a28));
329 writel(0x01010404, RCB_REG(0x3a2c));
330 writel(0x01040000, RCB_REG(0x3a80));
331 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
332 /* SATA 2/3 disabled */
333 setbits_le32(RCB_REG(0x3a84), 1 << 24);
334 /* SATA 4/5 disabled */
335 setbits_le32(RCB_REG(0x3a88), 1 << 0);
336 writel(0x00000001, RCB_REG(0x3a6c));
337 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
338 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
339 setbits_le32(RCB_REG(0x33a4), (1 << 0));
340 writel(0, RCB_REG(0x33c8));
341 setbits_le32(RCB_REG(0x21b0), 0xf);
342 }
343
enable_hpet(void)344 static void enable_hpet(void)
345 {
346 /* Move HPET to default address 0xfed00000 and enable it */
347 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
348 }
349
enable_clock_gating(struct udevice * pch)350 static void enable_clock_gating(struct udevice *pch)
351 {
352 u32 reg32;
353 u16 reg16;
354
355 setbits_le32(RCB_REG(0x2234), 0xf);
356
357 dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
358 reg16 |= (1 << 2) | (1 << 11);
359 dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
360
361 pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
362 pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
363 pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
364 pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
365
366 reg32 = readl(RCB_REG(CG));
367 reg32 |= (1 << 31);
368 reg32 |= (1 << 29) | (1 << 28);
369 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
370 reg32 |= (1 << 16);
371 reg32 |= (1 << 17);
372 reg32 |= (1 << 18);
373 reg32 |= (1 << 22);
374 reg32 |= (1 << 23);
375 reg32 &= ~(1 << 20);
376 reg32 |= (1 << 19);
377 reg32 |= (1 << 0);
378 reg32 |= (0xf << 1);
379 writel(reg32, RCB_REG(CG));
380
381 setbits_le32(RCB_REG(0x38c0), 0x7);
382 setbits_le32(RCB_REG(0x36d4), 0x6680c004);
383 setbits_le32(RCB_REG(0x3564), 0x3);
384 }
385
pch_disable_smm_only_flashing(struct udevice * pch)386 static void pch_disable_smm_only_flashing(struct udevice *pch)
387 {
388 u8 reg8;
389
390 debug("Enabling BIOS updates outside of SMM... ");
391 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
392 reg8 &= ~(1 << 5);
393 dm_pci_write_config8(pch, 0xdc, reg8);
394 }
395
pch_fixups(struct udevice * pch)396 static void pch_fixups(struct udevice *pch)
397 {
398 u8 gen_pmcon_2;
399
400 /* Indicate DRAM init done for MRC S3 to know it can resume */
401 dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
402 gen_pmcon_2 |= (1 << 7);
403 dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
404
405 /* Enable DMI ASPM in the PCH */
406 clrbits_le32(RCB_REG(0x2304), 1 << 10);
407 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
408 setbits_le32(RCB_REG(0x21a8), 0x3);
409 }
410
set_spi_speed(void)411 static void set_spi_speed(void)
412 {
413 u32 fdod;
414
415 /* Observe SPI Descriptor Component Section 0 */
416 writel(0x1000, RCB_REG(SPI_DESC_COMP0));
417
418 /* Extract the1 Write/Erase SPI Frequency from descriptor */
419 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
420 fdod >>= 24;
421 fdod &= 7;
422
423 /* Set Software Sequence frequency to match */
424 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
425 }
426
lpc_init_extra(struct udevice * dev)427 static int lpc_init_extra(struct udevice *dev)
428 {
429 struct udevice *pch = dev->parent;
430
431 debug("pch: lpc_init\n");
432 dm_pci_write_bar32(pch, 0, 0);
433 dm_pci_write_bar32(pch, 1, 0xff800000);
434 dm_pci_write_bar32(pch, 2, 0xfec00000);
435 dm_pci_write_bar32(pch, 3, 0x800);
436 dm_pci_write_bar32(pch, 4, 0x900);
437
438 /* Set the value for PCI command register. */
439 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
440
441 /* IO APIC initialization. */
442 pch_enable_apic(pch);
443
444 pch_enable_serial_irqs(pch);
445
446 /* Setup the PIRQ. */
447 pch_pirq_init(pch);
448
449 /* Setup power options. */
450 pch_power_options(pch);
451
452 /* Initialize power management */
453 switch (pch_silicon_type(pch)) {
454 case PCH_TYPE_CPT: /* CougarPoint */
455 cpt_pm_init(pch);
456 break;
457 case PCH_TYPE_PPT: /* PantherPoint */
458 ppt_pm_init(pch);
459 break;
460 default:
461 printf("Unknown Chipset: %s\n", pch->name);
462 return -ENOSYS;
463 }
464
465 /* Initialize the real time clock. */
466 pch_rtc_init(pch);
467
468 /* Initialize the High Precision Event Timers, if present. */
469 enable_hpet();
470
471 /* Initialize Clock Gating */
472 enable_clock_gating(pch);
473
474 pch_disable_smm_only_flashing(pch);
475
476 pch_fixups(pch);
477
478 return 0;
479 }
480
bd82x6x_lpc_early_init(struct udevice * dev)481 static int bd82x6x_lpc_early_init(struct udevice *dev)
482 {
483 set_spi_speed();
484
485 /* Setting up Southbridge. In the northbridge code. */
486 debug("Setting up static southbridge registers\n");
487 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
488 RCB_BASE_ADDRESS | 1);
489 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
490
491 /* Enable ACPI BAR */
492 dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
493
494 debug("Disabling watchdog reboot\n");
495 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
496 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
497
498 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
499 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
500
501 return 0;
502 }
503
bd82x6x_lpc_probe(struct udevice * dev)504 static int bd82x6x_lpc_probe(struct udevice *dev)
505 {
506 int ret;
507
508 if (!(gd->flags & GD_FLG_RELOC)) {
509 ret = lpc_common_early_init(dev);
510 if (ret) {
511 debug("%s: lpc_early_init() failed\n", __func__);
512 return ret;
513 }
514
515 return bd82x6x_lpc_early_init(dev);
516 }
517
518 return lpc_init_extra(dev);
519 }
520
521 static const struct udevice_id bd82x6x_lpc_ids[] = {
522 { .compatible = "intel,bd82x6x-lpc" },
523 { }
524 };
525
526 U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
527 .name = "lpc",
528 .id = UCLASS_LPC,
529 .of_match = bd82x6x_lpc_ids,
530 .probe = bd82x6x_lpc_probe,
531 };
532