1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From Coreboot
4 * Copyright (C) 2008-2009 coresystems GmbH
5 */
6
7 #include <common.h>
8 #include <ahci.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <log.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <asm/pch_common.h>
15 #include <asm/pci.h>
16 #include <asm/arch/pch.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
common_sata_init(struct udevice * dev,unsigned int port_map)20 static void common_sata_init(struct udevice *dev, unsigned int port_map)
21 {
22 u32 reg32;
23 u16 reg16;
24
25 /* Set IDE I/O Configuration */
26 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
27 dm_pci_write_config32(dev, IDE_CONFIG, reg32);
28
29 /* Port enable */
30 dm_pci_read_config16(dev, 0x92, ®16);
31 reg16 &= ~0x3f;
32 reg16 |= port_map;
33 dm_pci_write_config16(dev, 0x92, reg16);
34
35 /* SATA Initialization register */
36 port_map &= 0xff;
37 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
38 }
39
bd82x6x_sata_init(struct udevice * dev,struct udevice * pch)40 static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
41 {
42 unsigned int port_map, speed_support, port_tx;
43 const void *blob = gd->fdt_blob;
44 int node = dev_of_offset(dev);
45 const char *mode;
46 u32 reg32;
47 u16 reg16;
48
49 debug("SATA: Initializing...\n");
50
51 /* SATA configuration */
52 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
53 speed_support = fdtdec_get_int(blob, node,
54 "sata_interface_speed_support", 0);
55
56 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
57 if (!mode || !strcmp(mode, "ahci")) {
58 ulong abar;
59
60 debug("SATA: Controller in AHCI mode\n");
61
62 /* Set timings */
63 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
64 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
65 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
66 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
67 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
68
69 /* Sync DMA */
70 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
71 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
72
73 common_sata_init(dev, 0x8000 | port_map);
74
75 /* Initialize AHCI memory-mapped space */
76 abar = dm_pci_read_bar32(dev, 5);
77 debug("ABAR: %08lx\n", abar);
78 /* CAP (HBA Capabilities) : enable power management */
79 reg32 = readl(abar + 0x00);
80 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
81 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
82 /* Set ISS, if available */
83 if (speed_support) {
84 reg32 &= ~0x00f00000;
85 reg32 |= (speed_support & 0x03) << 20;
86 }
87 writel(reg32, abar + 0x00);
88 /* PI (Ports implemented) */
89 writel(port_map, abar + 0x0c);
90 (void) readl(abar + 0x0c); /* Read back 1 */
91 (void) readl(abar + 0x0c); /* Read back 2 */
92 /* CAP2 (HBA Capabilities Extended)*/
93 reg32 = readl(abar + 0x24);
94 reg32 &= ~0x00000002;
95 writel(reg32, abar + 0x24);
96 /* VSP (Vendor Specific Register */
97 reg32 = readl(abar + 0xa0);
98 reg32 &= ~0x00000005;
99 writel(reg32, abar + 0xa0);
100 } else if (!strcmp(mode, "combined")) {
101 debug("SATA: Controller in combined mode\n");
102
103 /* No AHCI: clear AHCI base */
104 dm_pci_write_bar32(dev, 5, 0x00000000);
105 /* And without AHCI BAR no memory decoding */
106 dm_pci_read_config16(dev, PCI_COMMAND, ®16);
107 reg16 &= ~PCI_COMMAND_MEMORY;
108 dm_pci_write_config16(dev, PCI_COMMAND, reg16);
109
110 dm_pci_write_config8(dev, 0x09, 0x80);
111
112 /* Set timings */
113 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
114 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
115 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
116 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
117 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
118
119 /* Sync DMA */
120 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
121 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
122
123 common_sata_init(dev, port_map);
124 } else {
125 debug("SATA: Controller in plain-ide mode\n");
126
127 /* No AHCI: clear AHCI base */
128 dm_pci_write_bar32(dev, 5, 0x00000000);
129
130 /* And without AHCI BAR no memory decoding */
131 dm_pci_read_config16(dev, PCI_COMMAND, ®16);
132 reg16 &= ~PCI_COMMAND_MEMORY;
133 dm_pci_write_config16(dev, PCI_COMMAND, reg16);
134
135 /*
136 * Native mode capable on both primary and secondary (0xa)
137 * OR'ed with enabled (0x50) = 0xf
138 */
139 dm_pci_write_config8(dev, 0x09, 0x8f);
140
141 /* Set timings */
142 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
143 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
144 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
145 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
146 IDE_SITRE | IDE_ISP_3_CLOCKS |
147 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
148
149 /* Sync DMA */
150 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
151 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
152
153 common_sata_init(dev, port_map);
154 }
155
156 /* Set Gen3 Transmitter settings if needed */
157 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
158 if (port_tx)
159 pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
160
161 port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
162 if (port_tx)
163 pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
164
165 /* Additional Programming Requirements */
166 pch_common_sir_write(dev, 0x04, 0x00001600);
167 pch_common_sir_write(dev, 0x28, 0xa0000033);
168 reg32 = pch_common_sir_read(dev, 0x54);
169 reg32 &= 0xff000000;
170 reg32 |= 0x5555aa;
171 pch_common_sir_write(dev, 0x54, reg32);
172 pch_common_sir_write(dev, 0x64, 0xcccc8484);
173 reg32 = pch_common_sir_read(dev, 0x68);
174 reg32 &= 0xffff0000;
175 reg32 |= 0xcccc;
176 pch_common_sir_write(dev, 0x68, reg32);
177 reg32 = pch_common_sir_read(dev, 0x78);
178 reg32 &= 0x0000ffff;
179 reg32 |= 0x88880000;
180 pch_common_sir_write(dev, 0x78, reg32);
181 pch_common_sir_write(dev, 0x84, 0x001c7000);
182 pch_common_sir_write(dev, 0x88, 0x88338822);
183 pch_common_sir_write(dev, 0xa0, 0x001c7000);
184 pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
185 pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
186 pch_common_sir_write(dev, 0xd4, 0x10000000);
187
188 pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
189 pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
190 }
191
bd82x6x_sata_enable(struct udevice * dev)192 static void bd82x6x_sata_enable(struct udevice *dev)
193 {
194 const void *blob = gd->fdt_blob;
195 int node = dev_of_offset(dev);
196 unsigned port_map;
197 const char *mode;
198 u16 map = 0;
199
200 /*
201 * Set SATA controller mode early so the resource allocator can
202 * properly assign IO/Memory resources for the controller.
203 */
204 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
205 if (mode && !strcmp(mode, "ahci"))
206 map = 0x0060;
207 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
208
209 map |= (port_map ^ 0x3f) << 8;
210 dm_pci_write_config16(dev, 0x90, map);
211 }
212
bd82x6x_sata_bind(struct udevice * dev)213 static int bd82x6x_sata_bind(struct udevice *dev)
214 {
215 struct udevice *scsi_dev;
216 int ret;
217
218 if (gd->flags & GD_FLG_RELOC) {
219 ret = ahci_bind_scsi(dev, &scsi_dev);
220 if (ret)
221 return ret;
222 }
223
224 return 0;
225 }
226
bd82x6x_sata_probe(struct udevice * dev)227 static int bd82x6x_sata_probe(struct udevice *dev)
228 {
229 struct udevice *pch;
230 int ret;
231
232 ret = uclass_first_device_err(UCLASS_PCH, &pch);
233 if (ret)
234 return ret;
235
236 if (!(gd->flags & GD_FLG_RELOC))
237 bd82x6x_sata_enable(dev);
238 else {
239 bd82x6x_sata_init(dev, pch);
240 ret = ahci_probe_scsi_pci(dev);
241 if (ret)
242 return ret;
243 }
244
245 return 0;
246 }
247
248 static const struct udevice_id bd82x6x_ahci_ids[] = {
249 { .compatible = "intel,pantherpoint-ahci" },
250 { }
251 };
252
253 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
254 .name = "ahci_ivybridge",
255 .id = UCLASS_AHCI,
256 .of_match = bd82x6x_ahci_ids,
257 .bind = bd82x6x_sata_bind,
258 .probe = bd82x6x_sata_probe,
259 };
260