1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2010,2011
5 * Graeme Russ, <graeme.russ@gmail.com>
6 *
7 * Portions from Coreboot mainboard/google/link/romstage.c
8 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <fdtdec.h>
16 #include <init.h>
17 #include <log.h>
18 #include <malloc.h>
19 #include <net.h>
20 #include <rtc.h>
21 #include <spi.h>
22 #include <spi_flash.h>
23 #include <syscon.h>
24 #include <sysreset.h>
25 #include <asm/cpu.h>
26 #include <asm/processor.h>
27 #include <asm/gpio.h>
28 #include <asm/global_data.h>
29 #include <asm/intel_regs.h>
30 #include <asm/mrccache.h>
31 #include <asm/mrc_common.h>
32 #include <asm/mtrr.h>
33 #include <asm/pci.h>
34 #include <asm/report_platform.h>
35 #include <asm/arch/me.h>
36 #include <asm/arch/pei_data.h>
37 #include <asm/arch/pch.h>
38 #include <asm/post.h>
39 #include <asm/arch/sandybridge.h>
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 #define CMOS_OFFSET_MRC_SEED 152
44 #define CMOS_OFFSET_MRC_SEED_S3 156
45 #define CMOS_OFFSET_MRC_SEED_CHK 160
46
board_get_usable_ram_top(ulong total_size)47 ulong board_get_usable_ram_top(ulong total_size)
48 {
49 return mrc_common_board_get_usable_ram_top(total_size);
50 }
51
dram_init_banksize(void)52 int dram_init_banksize(void)
53 {
54 mrc_common_dram_init_banksize();
55
56 return 0;
57 }
58
read_seed_from_cmos(struct pei_data * pei_data)59 static int read_seed_from_cmos(struct pei_data *pei_data)
60 {
61 u16 c1, c2, checksum, seed_checksum;
62 struct udevice *dev;
63 int ret = 0;
64
65 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
66 if (ret) {
67 debug("Cannot find RTC: err=%d\n", ret);
68 return -ENODEV;
69 }
70
71 /*
72 * Read scrambler seeds from CMOS RAM. We don't want to store them in
73 * SPI flash since they change on every boot and that would wear down
74 * the flash too much. So we store these in CMOS and the large MRC
75 * data in SPI flash.
76 */
77 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
78 if (!ret) {
79 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3,
80 &pei_data->scrambler_seed_s3);
81 }
82 if (ret) {
83 debug("Failed to read from RTC %s\n", dev->name);
84 return ret;
85 }
86
87 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
88 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
89 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
90 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
91
92 /* Compute seed checksum and compare */
93 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
94 sizeof(u32));
95 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
96 sizeof(u32));
97 checksum = add_ip_checksums(sizeof(u32), c1, c2);
98
99 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
100 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
101
102 if (checksum != seed_checksum) {
103 debug("%s: invalid seed checksum\n", __func__);
104 pei_data->scrambler_seed = 0;
105 pei_data->scrambler_seed_s3 = 0;
106 return -EINVAL;
107 }
108
109 return 0;
110 }
111
prepare_mrc_cache(struct pei_data * pei_data)112 static int prepare_mrc_cache(struct pei_data *pei_data)
113 {
114 struct mrc_data_container *mrc_cache;
115 struct mrc_region entry;
116 int ret;
117
118 ret = read_seed_from_cmos(pei_data);
119 if (ret)
120 return ret;
121 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
122 if (ret)
123 return ret;
124 mrc_cache = mrccache_find_current(&entry);
125 if (!mrc_cache)
126 return -ENOENT;
127
128 pei_data->mrc_input = mrc_cache->data;
129 pei_data->mrc_input_len = mrc_cache->data_size;
130 debug("%s: at %p, size %x checksum %04x\n", __func__,
131 pei_data->mrc_input, pei_data->mrc_input_len,
132 mrc_cache->checksum);
133
134 return 0;
135 }
136
write_seeds_to_cmos(struct pei_data * pei_data)137 static int write_seeds_to_cmos(struct pei_data *pei_data)
138 {
139 u16 c1, c2, checksum;
140 struct udevice *dev;
141 int ret = 0;
142
143 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
144 if (ret) {
145 debug("Cannot find RTC: err=%d\n", ret);
146 return -ENODEV;
147 }
148
149 /* Save the MRC seed values to CMOS */
150 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
151 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
152 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
153
154 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
155 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
156 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
157
158 /* Save a simple checksum of the seed values */
159 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
160 sizeof(u32));
161 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
162 sizeof(u32));
163 checksum = add_ip_checksums(sizeof(u32), c1, c2);
164
165 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
166 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
167
168 return 0;
169 }
170
171 /* Use this hook to save our SDRAM parameters */
misc_init_r(void)172 int misc_init_r(void)
173 {
174 int ret;
175
176 ret = mrccache_save();
177 if (ret)
178 printf("Unable to save MRC data: %d\n", ret);
179
180 return 0;
181 }
182
post_system_agent_init(struct udevice * dev,struct udevice * me_dev,struct pei_data * pei_data)183 static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
184 struct pei_data *pei_data)
185 {
186 uint16_t done;
187
188 /*
189 * Send ME init done for SandyBridge here. This is done inside the
190 * SystemAgent binary on IvyBridge
191 */
192 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
193 done &= BASE_REV_MASK;
194 if (BASE_REV_SNB == done)
195 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
196 else
197 intel_me_status(me_dev);
198
199 /* If PCIe init is skipped, set the PEG clock gating */
200 if (!pei_data->pcie_init)
201 setbits_le32(MCHBAR_REG(0x7010), 1);
202 }
203
recovery_mode_enabled(void)204 static int recovery_mode_enabled(void)
205 {
206 return false;
207 }
208
copy_spd(struct udevice * dev,struct pei_data * peid)209 static int copy_spd(struct udevice *dev, struct pei_data *peid)
210 {
211 const void *data;
212 int ret;
213
214 ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
215 if (ret) {
216 debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
217 return ret;
218 }
219
220 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
221
222 return 0;
223 }
224
225 /**
226 * sdram_find() - Find available memory
227 *
228 * This is a bit complicated since on x86 there are system memory holes all
229 * over the place. We create a list of available memory blocks
230 *
231 * @dev: Northbridge device
232 */
sdram_find(struct udevice * dev)233 static int sdram_find(struct udevice *dev)
234 {
235 struct memory_info *info = &gd->arch.meminfo;
236 uint32_t tseg_base, uma_size, tolud;
237 uint64_t tom, me_base, touud;
238 uint64_t uma_memory_base = 0;
239 unsigned long long tomk;
240 uint16_t ggc;
241 u32 val;
242
243 /* Total Memory 2GB example:
244 *
245 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
246 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
247 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
248 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
249 * 7f200000 2034MB TOLUD
250 * 7f800000 2040MB MEBASE
251 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
252 * 80000000 2048MB TOM
253 * 100000000 4096MB-4102MB 6MB RAM (writeback)
254 *
255 * Total Memory 4GB example:
256 *
257 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
258 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
259 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
260 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
261 * afa00000 2810MB TOLUD
262 * ff800000 4088MB MEBASE
263 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
264 * 100000000 4096MB TOM
265 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
266 * 14fe00000 5368MB TOUUD
267 */
268
269 /* Top of Upper Usable DRAM, including remap */
270 dm_pci_read_config32(dev, TOUUD + 4, &val);
271 touud = (uint64_t)val << 32;
272 dm_pci_read_config32(dev, TOUUD, &val);
273 touud |= val;
274
275 /* Top of Lower Usable DRAM */
276 dm_pci_read_config32(dev, TOLUD, &tolud);
277
278 /* Top of Memory - does not account for any UMA */
279 dm_pci_read_config32(dev, 0xa4, &val);
280 tom = (uint64_t)val << 32;
281 dm_pci_read_config32(dev, 0xa0, &val);
282 tom |= val;
283
284 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
285
286 /* ME UMA needs excluding if total memory <4GB */
287 dm_pci_read_config32(dev, 0x74, &val);
288 me_base = (uint64_t)val << 32;
289 dm_pci_read_config32(dev, 0x70, &val);
290 me_base |= val;
291
292 debug("MEBASE %llx\n", me_base);
293
294 /* TODO: Get rid of all this shifting by 10 bits */
295 tomk = tolud >> 10;
296 if (me_base == tolud) {
297 /* ME is from MEBASE-TOM */
298 uma_size = (tom - me_base) >> 10;
299 /* Increment TOLUD to account for ME as RAM */
300 tolud += uma_size << 10;
301 /* UMA starts at old TOLUD */
302 uma_memory_base = tomk * 1024ULL;
303 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
304 }
305
306 /* Graphics memory comes next */
307 dm_pci_read_config16(dev, GGC, &ggc);
308 if (!(ggc & 2)) {
309 debug("IGD decoded, subtracting ");
310
311 /* Graphics memory */
312 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
313 debug("%uM UMA", uma_size >> 10);
314 tomk -= uma_size;
315 uma_memory_base = tomk * 1024ULL;
316
317 /* GTT Graphics Stolen Memory Size (GGMS) */
318 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
319 tomk -= uma_size;
320 uma_memory_base = tomk * 1024ULL;
321 debug(" and %uM GTT\n", uma_size >> 10);
322 }
323
324 /* Calculate TSEG size from its base which must be below GTT */
325 dm_pci_read_config32(dev, 0xb8, &tseg_base);
326 uma_size = (uma_memory_base - tseg_base) >> 10;
327 tomk -= uma_size;
328 uma_memory_base = tomk * 1024ULL;
329 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
330
331 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
332
333 /* Report the memory regions */
334 mrc_add_memory_area(info, 1 << 20, 2 << 28);
335 mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
336 mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
337 mrc_add_memory_area(info, 1ULL << 32, touud);
338
339 /* Add MTRRs for memory */
340 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
341 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
342 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
343 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
344 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
345 32 << 20);
346
347 /*
348 * If >= 4GB installed then memory from TOLUD to 4GB
349 * is remapped above TOM, TOUUD will account for both
350 */
351 if (touud > (1ULL << 32ULL)) {
352 debug("Available memory above 4GB: %lluM\n",
353 (touud >> 20) - 4096);
354 }
355
356 return 0;
357 }
358
rcba_config(void)359 static void rcba_config(void)
360 {
361 /*
362 * GFX INTA -> PIRQA (MSI)
363 * D28IP_P3IP WLAN INTA -> PIRQB
364 * D29IP_E1P EHCI1 INTA -> PIRQD
365 * D26IP_E2P EHCI2 INTA -> PIRQF
366 * D31IP_SIP SATA INTA -> PIRQF (MSI)
367 * D31IP_SMIP SMBUS INTB -> PIRQH
368 * D31IP_TTIP THRT INTC -> PIRQA
369 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
370 *
371 * TRACKPAD -> PIRQE (Edge Triggered)
372 * TOUCHSCREEN -> PIRQG (Edge Triggered)
373 */
374
375 /* Device interrupt pin register (board specific) */
376 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
377 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
378 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
379 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
380 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
381 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
382 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
383 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
384 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
385
386 /* Device interrupt route registers */
387 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
388 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
389 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
390 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
391 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
392 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
393 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
394
395 /* Enable IOAPIC (generic) */
396 writew(0x0100, RCB_REG(OIC));
397 /* PCH BWG says to read back the IOAPIC enable register */
398 (void)readw(RCB_REG(OIC));
399
400 /* Disable unused devices (board specific) */
401 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
402 }
403
dram_init(void)404 int dram_init(void)
405 {
406 struct pei_data _pei_data __aligned(8) = {
407 .pei_version = PEI_VERSION,
408 .mchbar = MCH_BASE_ADDRESS,
409 .dmibar = DEFAULT_DMIBAR,
410 .epbar = DEFAULT_EPBAR,
411 .pciexbar = CONFIG_PCIE_ECAM_BASE,
412 .smbusbar = SMBUS_IO_BASE,
413 .wdbbar = 0x4000000,
414 .wdbsize = 0x1000,
415 .hpet_address = CONFIG_HPET_ADDRESS,
416 .rcba = DEFAULT_RCBABASE,
417 .pmbase = DEFAULT_PMBASE,
418 .gpiobase = DEFAULT_GPIOBASE,
419 .thermalbase = 0xfed08000,
420 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
421 .tseg_size = CONFIG_SMM_TSEG_SIZE,
422 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
423 .ec_present = 1,
424 .ddr3lv_support = 1,
425 /*
426 * 0 = leave channel enabled
427 * 1 = disable dimm 0 on channel
428 * 2 = disable dimm 1 on channel
429 * 3 = disable dimm 0+1 on channel
430 */
431 .dimm_channel0_disabled = 2,
432 .dimm_channel1_disabled = 2,
433 .max_ddr3_freq = 1600,
434 .usb_port_config = {
435 /*
436 * Empty and onboard Ports 0-7, set to un-used pin
437 * OC3
438 */
439 { 0, 3, 0x0000 }, /* P0= Empty */
440 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
441 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
442 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
443 { 0, 3, 0x0000 }, /* P4= Empty */
444 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
445 { 0, 3, 0x0000 }, /* P6= Empty */
446 { 0, 3, 0x0000 }, /* P7= Empty */
447 /*
448 * Empty and onboard Ports 8-13, set to un-used pin
449 * OC4
450 */
451 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
452 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
453 { 0, 4, 0x0000 }, /* P10= Empty */
454 { 0, 4, 0x0000 }, /* P11= Empty */
455 { 0, 4, 0x0000 }, /* P12= Empty */
456 { 0, 4, 0x0000 }, /* P13= Empty */
457 },
458 };
459 struct pei_data *pei_data = &_pei_data;
460 struct udevice *dev, *me_dev;
461 int ret;
462
463 /* We need the pinctrl set up early */
464 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
465 if (ret) {
466 debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
467 return ret;
468 }
469
470 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
471 if (ret) {
472 debug("%s: Could not get northbridge (ret=%d)\n", __func__,
473 ret);
474 return ret;
475 }
476 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
477 if (ret) {
478 debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
479 return ret;
480 }
481 ret = copy_spd(dev, pei_data);
482 if (ret) {
483 debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
484 return ret;
485 }
486 pei_data->boot_mode = gd->arch.pei_boot_mode;
487 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
488 debug("mrc_input %p\n", pei_data->mrc_input);
489
490 /*
491 * Do not pass MRC data in for recovery mode boot,
492 * Always pass it in for S3 resume.
493 */
494 if (!recovery_mode_enabled() ||
495 pei_data->boot_mode == PEI_BOOT_RESUME) {
496 ret = prepare_mrc_cache(pei_data);
497 if (ret)
498 debug("prepare_mrc_cache failed: %d\n", ret);
499 }
500
501 /* If MRC data is not found we cannot continue S3 resume. */
502 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
503 debug("Giving up in sdram_initialize: No MRC data\n");
504 sysreset_walk_halt(SYSRESET_COLD);
505 }
506
507 /* Pass console handler in pei_data */
508 pei_data->tx_byte = sdram_console_tx_byte;
509
510 /* Wait for ME to be ready */
511 ret = intel_early_me_init(me_dev);
512 if (ret) {
513 debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
514 return ret;
515 }
516 ret = intel_early_me_uma_size(me_dev);
517 if (ret < 0) {
518 debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
519 return ret;
520 }
521
522 ret = mrc_common_init(dev, pei_data, false);
523 if (ret) {
524 debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
525 return ret;
526 }
527
528 ret = sdram_find(dev);
529 if (ret) {
530 debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
531 return ret;
532 }
533 gd->ram_size = gd->arch.meminfo.total_32bit_memory;
534
535 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
536 pei_data->mrc_output);
537
538 post_system_agent_init(dev, me_dev, pei_data);
539 report_memory_config();
540
541 /* S3 resume: don't save scrambler seed or MRC data */
542 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
543 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
544
545 /*
546 * This will be copied to SDRAM in reserve_arch(), then written
547 * to SPI flash in mrccache_save()
548 */
549 mrc->buf = (char *)pei_data->mrc_output;
550 mrc->len = pei_data->mrc_output_len;
551 ret = write_seeds_to_cmos(pei_data);
552 if (ret)
553 debug("Failed to write seeds to CMOS: %d\n", ret);
554 }
555
556 writew(0xCAFE, MCHBAR_REG(SSKPD));
557 if (ret)
558 return ret;
559
560 rcba_config();
561
562 return 0;
563 }
564