1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on board/freescale/p1_p2_rdb_pc/spl.c
6 * original copyright follows:
7 * Copyright 2013 Freescale Semiconductor, Inc.
8 */
9
10 #include <common.h>
11 #include <clock_legacy.h>
12 #include <console.h>
13 #include <env.h>
14 #include <env_internal.h>
15 #include <init.h>
16 #include <ns16550.h>
17 #include <malloc.h>
18 #include <mmc.h>
19 #include <nand.h>
20 #include <i2c.h>
21 #include <fsl_esdhc.h>
22 #include <spi_flash.h>
23 #include <asm/global_data.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 static const u32 sysclk_tbl[] = {
28 66666000, 7499900, 83332500, 8999900,
29 99999000, 11111000, 12499800, 13333200
30 };
31
get_effective_memsize(void)32 phys_size_t get_effective_memsize(void)
33 {
34 return CONFIG_SYS_L2_SIZE;
35 }
36
board_init_f(ulong bootflag)37 void board_init_f(ulong bootflag)
38 {
39 u32 plat_ratio, bus_clk;
40 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
41
42 console_init_f();
43
44 /* Set pmuxcr to allow both i2c1 and i2c2 */
45 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
46 setbits_be32(&gur->pmuxcr,
47 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
48
49 /* Read back the register to synchronize the write. */
50 in_be32(&gur->pmuxcr);
51
52 #ifdef CONFIG_SPL_SPI_BOOT
53 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
54 #endif
55
56 /* initialize selected port with appropriate baud rate */
57 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
58 plat_ratio >>= 1;
59 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
60 gd->bus_clk = bus_clk;
61
62 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
63 bus_clk / 16 / CONFIG_BAUDRATE);
64 #ifdef CONFIG_SPL_MMC_BOOT
65 puts("\nSD boot...\n");
66 #elif defined(CONFIG_SPL_SPI_BOOT)
67 puts("\nSPI Flash boot...\n");
68 #endif
69
70 /* copy code to RAM and jump to it - this should not return */
71 /* NOTE - code has to be copied out of NAND buffer before
72 * other blocks can be read.
73 */
74 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
75 }
76
board_init_r(gd_t * gd,ulong dest_addr)77 void board_init_r(gd_t *gd, ulong dest_addr)
78 {
79 /* Pointer is writable since we allocated a register for it */
80 gd = (gd_t *)CONFIG_SPL_GD_ADDR;
81 struct bd_info *bd;
82
83 memset(gd, 0, sizeof(gd_t));
84 bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
85 memset(bd, 0, sizeof(struct bd_info));
86 gd->bd = bd;
87
88 arch_cpu_init();
89 get_clocks();
90 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
91 CONFIG_SPL_RELOC_MALLOC_SIZE);
92
93 #ifndef CONFIG_SPL_NAND_BOOT
94 env_init();
95 #endif
96 #ifdef CONFIG_SPL_MMC_BOOT
97 mmc_initialize(bd);
98 #endif
99 /* relocate environment function pointers etc. */
100 #ifdef CONFIG_SPL_NAND_BOOT
101 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
102 (uchar *)CONFIG_ENV_ADDR);
103 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
104 gd->env_valid = ENV_VALID;
105 #else
106 env_relocate();
107 #endif
108
109 #ifdef CONFIG_SYS_I2C
110 i2c_init_all();
111 #else
112 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
113 #endif
114
115 dram_init();
116 #ifdef CONFIG_SPL_NAND_BOOT
117 puts("Tertiary program loader running in sram...");
118 #else
119 puts("Second program loader running in sram...\n");
120 #endif
121
122 #ifdef CONFIG_SPL_MMC_BOOT
123 mmc_boot();
124 #elif defined(CONFIG_SPL_NAND_BOOT)
125 nand_boot();
126 #endif
127 }
128