1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
5 *
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <i2c.h>
13 #include <init.h>
14 #include <log.h>
15 #include <miiphy.h>
16 #include <net.h>
17 #include <netdev.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/soc.h>
22 #include <dm/uclass.h>
23 #include <fdt_support.h>
24 #include <time.h>
25 #include <linux/bitops.h>
26 #include <u-boot/crc.h>
27 # include <atsha204a-i2c.h>
28
29 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
30 #include <../serdes/a38x/high_speed_env_spec.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
35
36 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
37 #define OMNIA_I2C_MCU_CHIP_LEN 1
38
39 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
40 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
41 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
42
43 enum mcu_commands {
44 CMD_GET_STATUS_WORD = 0x01,
45 CMD_GET_RESET = 0x09,
46 CMD_WATCHDOG_STATE = 0x0b,
47 };
48
49 enum status_word_bits {
50 CARD_DET_STSBIT = 0x0010,
51 MSATA_IND_STSBIT = 0x0020,
52 };
53
54 #define OMNIA_ATSHA204_OTP_VERSION 0
55 #define OMNIA_ATSHA204_OTP_SERIAL 1
56 #define OMNIA_ATSHA204_OTP_MAC0 3
57 #define OMNIA_ATSHA204_OTP_MAC1 4
58
59 /*
60 * Those values and defines are taken from the Marvell U-Boot version
61 * "u-boot-2013.01-2014_T3.0"
62 */
63 #define OMNIA_GPP_OUT_ENA_LOW \
64 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
65 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
66 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
67 #define OMNIA_GPP_OUT_ENA_MID \
68 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
69 BIT(16) | BIT(17) | BIT(18)))
70
71 #define OMNIA_GPP_OUT_VAL_LOW 0x0
72 #define OMNIA_GPP_OUT_VAL_MID 0x0
73 #define OMNIA_GPP_POL_LOW 0x0
74 #define OMNIA_GPP_POL_MID 0x0
75
76 static struct serdes_map board_serdes_map_pex[] = {
77 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
78 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
79 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
80 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
81 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
82 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
83 };
84
85 static struct serdes_map board_serdes_map_sata[] = {
86 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
87 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
88 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
89 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
90 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
91 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
92 };
93
omnia_get_i2c_chip(const char * name,uint addr,uint offset_len)94 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
95 uint offset_len)
96 {
97 struct udevice *bus, *dev;
98 int ret;
99
100 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
101 if (ret) {
102 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
103 OMNIA_I2C_BUS_NAME, ret);
104 return NULL;
105 }
106
107 ret = i2c_get_chip(bus, addr, offset_len, &dev);
108 if (ret) {
109 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
110 name, ret);
111 return NULL;
112 }
113
114 return dev;
115 }
116
omnia_mcu_read(u8 cmd,void * buf,int len)117 static int omnia_mcu_read(u8 cmd, void *buf, int len)
118 {
119 struct udevice *chip;
120
121 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
122 OMNIA_I2C_MCU_CHIP_LEN);
123 if (!chip)
124 return -ENODEV;
125
126 return dm_i2c_read(chip, cmd, buf, len);
127 }
128
129 #ifndef CONFIG_SPL_BUILD
omnia_mcu_write(u8 cmd,const void * buf,int len)130 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
131 {
132 struct udevice *chip;
133
134 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
135 OMNIA_I2C_MCU_CHIP_LEN);
136 if (!chip)
137 return -ENODEV;
138
139 return dm_i2c_write(chip, cmd, buf, len);
140 }
141
disable_mcu_watchdog(void)142 static bool disable_mcu_watchdog(void)
143 {
144 int ret;
145
146 puts("Disabling MCU watchdog... ");
147
148 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
149 if (ret) {
150 printf("omnia_mcu_write failed: %i\n", ret);
151 return false;
152 }
153
154 puts("disabled\n");
155
156 return true;
157 }
158 #endif
159
omnia_detect_sata(void)160 static bool omnia_detect_sata(void)
161 {
162 int ret;
163 u16 stsword;
164
165 puts("MiniPCIe/mSATA card detection... ");
166
167 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
168 if (ret) {
169 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
170 ret);
171 return false;
172 }
173
174 if (!(stsword & CARD_DET_STSBIT)) {
175 puts("none\n");
176 return false;
177 }
178
179 if (stsword & MSATA_IND_STSBIT)
180 puts("mSATA\n");
181 else
182 puts("MiniPCIe\n");
183
184 return stsword & MSATA_IND_STSBIT ? true : false;
185 }
186
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)187 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
188 {
189 if (omnia_detect_sata()) {
190 *serdes_map_array = board_serdes_map_sata;
191 *count = ARRAY_SIZE(board_serdes_map_sata);
192 } else {
193 *serdes_map_array = board_serdes_map_pex;
194 *count = ARRAY_SIZE(board_serdes_map_pex);
195 }
196
197 return 0;
198 }
199
200 struct omnia_eeprom {
201 u32 magic;
202 u32 ramsize;
203 char region[4];
204 u32 crc;
205 };
206
omnia_read_eeprom(struct omnia_eeprom * oep)207 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
208 {
209 struct udevice *chip;
210 u32 crc;
211 int ret;
212
213 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
214 OMNIA_I2C_EEPROM_CHIP_LEN);
215
216 if (!chip)
217 return false;
218
219 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
220 if (ret) {
221 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
222 return false;
223 }
224
225 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
226 printf("bad EEPROM magic number (%08x, should be %08x)\n",
227 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
228 return false;
229 }
230
231 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
232 if (crc != oep->crc) {
233 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
234 oep->crc, crc);
235 return false;
236 }
237
238 return true;
239 }
240
omnia_get_ram_size_gb(void)241 static int omnia_get_ram_size_gb(void)
242 {
243 static int ram_size;
244 struct omnia_eeprom oep;
245
246 if (!ram_size) {
247 /* Get the board config from EEPROM */
248 if (omnia_read_eeprom(&oep)) {
249 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
250
251 if (oep.ramsize == 0x2)
252 ram_size = 2;
253 else
254 ram_size = 1;
255 } else {
256 /* Hardcoded fallback */
257 puts("Memory config from EEPROM read failed!\n");
258 puts("Falling back to default 1 GiB!\n");
259 ram_size = 1;
260 }
261 }
262
263 return ram_size;
264 }
265
266 /*
267 * Define the DDR layout / topology here in the board file. This will
268 * be used by the DDR3 init code in the SPL U-Boot version to configure
269 * the DDR3 controller.
270 */
271 static struct mv_ddr_topology_map board_topology_map_1g = {
272 DEBUG_LEVEL_ERROR,
273 0x1, /* active interfaces */
274 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
275 { { { {0x1, 0, 0, 0},
276 {0x1, 0, 0, 0},
277 {0x1, 0, 0, 0},
278 {0x1, 0, 0, 0},
279 {0x1, 0, 0, 0} },
280 SPEED_BIN_DDR_1600K, /* speed_bin */
281 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
282 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
283 MV_DDR_FREQ_800, /* frequency */
284 0, 0, /* cas_wl cas_l */
285 MV_DDR_TEMP_NORMAL, /* temperature */
286 MV_DDR_TIM_2T} }, /* timing */
287 BUS_MASK_32BIT, /* Busses mask */
288 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
289 NOT_COMBINED, /* ddr twin-die combined */
290 { {0} }, /* raw spd data */
291 {0} /* timing parameters */
292 };
293
294 static struct mv_ddr_topology_map board_topology_map_2g = {
295 DEBUG_LEVEL_ERROR,
296 0x1, /* active interfaces */
297 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
298 { { { {0x1, 0, 0, 0},
299 {0x1, 0, 0, 0},
300 {0x1, 0, 0, 0},
301 {0x1, 0, 0, 0},
302 {0x1, 0, 0, 0} },
303 SPEED_BIN_DDR_1600K, /* speed_bin */
304 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
305 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
306 MV_DDR_FREQ_800, /* frequency */
307 0, 0, /* cas_wl cas_l */
308 MV_DDR_TEMP_NORMAL, /* temperature */
309 MV_DDR_TIM_2T} }, /* timing */
310 BUS_MASK_32BIT, /* Busses mask */
311 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
312 NOT_COMBINED, /* ddr twin-die combined */
313 { {0} }, /* raw spd data */
314 {0} /* timing parameters */
315 };
316
mv_ddr_topology_map_get(void)317 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
318 {
319 if (omnia_get_ram_size_gb() == 2)
320 return &board_topology_map_2g;
321 else
322 return &board_topology_map_1g;
323 }
324
325 #ifndef CONFIG_SPL_BUILD
set_regdomain(void)326 static int set_regdomain(void)
327 {
328 struct omnia_eeprom oep;
329 char rd[3] = {' ', ' ', 0};
330
331 if (omnia_read_eeprom(&oep))
332 memcpy(rd, &oep.region, 2);
333 else
334 puts("EEPROM regdomain read failed.\n");
335
336 printf("Regdomain set to %s\n", rd);
337 return env_set("regdomain", rd);
338 }
339
340 /*
341 * default factory reset bootcommand on Omnia first sets all the front LEDs
342 * to green and then tries to load the rescue image from SPI flash memory and
343 * boot it
344 */
345 #define OMNIA_FACTORY_RESET_BOOTCMD \
346 "i2c dev 2; " \
347 "i2c mw 0x2a.1 0x3 0x1c 1; " \
348 "i2c mw 0x2a.1 0x4 0x1c 1; " \
349 "mw.l 0x01000000 0x00ff000c; " \
350 "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
351 "setenv bootargs \"earlyprintk console=ttyS0,115200" \
352 " omniarescue=$omnia_reset\"; " \
353 "sf probe; " \
354 "sf read 0x1000000 0x100000 0x700000; " \
355 "bootm 0x1000000; " \
356 "bootz 0x1000000"
357
handle_reset_button(void)358 static void handle_reset_button(void)
359 {
360 int ret;
361 u8 reset_status;
362
363 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
364 if (ret) {
365 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
366 ret);
367 return;
368 }
369
370 env_set_ulong("omnia_reset", reset_status);
371
372 if (reset_status) {
373 printf("RESET button was pressed, overwriting bootcmd!\n");
374 env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
375 }
376 }
377 #endif
378
board_early_init_f(void)379 int board_early_init_f(void)
380 {
381 /* Configure MPP */
382 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
383 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
384 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
385 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
386 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
387 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
388 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
389 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
390
391 /* Set GPP Out value */
392 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
393 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
394
395 /* Set GPP Polarity */
396 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
397 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
398
399 /* Set GPP Out Enable */
400 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
401 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
402
403 return 0;
404 }
405
board_init(void)406 int board_init(void)
407 {
408 /* address of boot parameters */
409 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
410
411 #ifndef CONFIG_SPL_BUILD
412 disable_mcu_watchdog();
413 #endif
414
415 return 0;
416 }
417
board_late_init(void)418 int board_late_init(void)
419 {
420 #ifndef CONFIG_SPL_BUILD
421 set_regdomain();
422 handle_reset_button();
423 #endif
424 pci_init();
425
426 return 0;
427 }
428
get_atsha204a_dev(void)429 static struct udevice *get_atsha204a_dev(void)
430 {
431 static struct udevice *dev;
432
433 if (dev)
434 return dev;
435
436 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
437 puts("Cannot find ATSHA204A on I2C bus!\n");
438 dev = NULL;
439 }
440
441 return dev;
442 }
443
checkboard(void)444 int checkboard(void)
445 {
446 u32 version_num, serial_num;
447 int err = 1;
448
449 struct udevice *dev = get_atsha204a_dev();
450
451 if (dev) {
452 err = atsha204a_wakeup(dev);
453 if (err)
454 goto out;
455
456 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
457 OMNIA_ATSHA204_OTP_VERSION,
458 (u8 *)&version_num);
459 if (err)
460 goto out;
461
462 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
463 OMNIA_ATSHA204_OTP_SERIAL,
464 (u8 *)&serial_num);
465 if (err)
466 goto out;
467
468 atsha204a_sleep(dev);
469 }
470
471 out:
472 printf("Turris Omnia:\n");
473 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
474 if (err)
475 printf(" Serial Number: unknown\n");
476 else
477 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
478 be32_to_cpu(serial_num));
479
480 return 0;
481 }
482
increment_mac(u8 * mac)483 static void increment_mac(u8 *mac)
484 {
485 int i;
486
487 for (i = 5; i >= 3; i--) {
488 mac[i] += 1;
489 if (mac[i])
490 break;
491 }
492 }
493
misc_init_r(void)494 int misc_init_r(void)
495 {
496 int err;
497 struct udevice *dev = get_atsha204a_dev();
498 u8 mac0[4], mac1[4], mac[6];
499
500 if (!dev)
501 goto out;
502
503 err = atsha204a_wakeup(dev);
504 if (err)
505 goto out;
506
507 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
508 OMNIA_ATSHA204_OTP_MAC0, mac0);
509 if (err)
510 goto out;
511
512 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
513 OMNIA_ATSHA204_OTP_MAC1, mac1);
514 if (err)
515 goto out;
516
517 atsha204a_sleep(dev);
518
519 mac[0] = mac0[1];
520 mac[1] = mac0[2];
521 mac[2] = mac0[3];
522 mac[3] = mac1[1];
523 mac[4] = mac1[2];
524 mac[5] = mac1[3];
525
526 if (is_valid_ethaddr(mac))
527 eth_env_set_enetaddr("eth1addr", mac);
528
529 increment_mac(mac);
530
531 if (is_valid_ethaddr(mac))
532 eth_env_set_enetaddr("eth2addr", mac);
533
534 increment_mac(mac);
535
536 if (is_valid_ethaddr(mac))
537 eth_env_set_enetaddr("ethaddr", mac);
538
539 out:
540 return 0;
541 }
542
543