1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 */
18 #include <common.h>
19 #include <bootstage.h>
20 #include <cpu_func.h>
21 #include <init.h>
22 #include <malloc.h>
23 #include <errno.h>
24 #include <net.h>
25 #include <netdev.h>
26 #include <asm/global_data.h>
27 #include <asm/io.h>
28 #include <asm/mach-types.h>
29 #include <asm/arch/systimer.h>
30 #include <asm/arch/sysctrl.h>
31 #include <asm/arch/wdt.h>
32 #include "../drivers/mmc/arm_pl180_mmci.h"
33
34 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
35 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
36
37 static void flash__init(void);
38 static void vexpress_timer_init(void);
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)42 void show_boot_progress(int progress)
43 {
44 printf("Boot reached stage %d\n", progress);
45 }
46 #endif
47
delay(ulong loops)48 static inline void delay(ulong loops)
49 {
50 __asm__ volatile ("1:\n"
51 "subs %0, %1, #1\n"
52 "bne 1b" : "=r" (loops) : "0" (loops));
53 }
54
board_init(void)55 int board_init(void)
56 {
57 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
58 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
59
60 icache_enable();
61 flash__init();
62 vexpress_timer_init();
63
64 return 0;
65 }
66
board_eth_init(struct bd_info * bis)67 int board_eth_init(struct bd_info *bis)
68 {
69 int rc = 0;
70 #ifdef CONFIG_SMC911X
71 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
72 #endif
73 return rc;
74 }
75
cpu_mmc_init(struct bd_info * bis)76 int cpu_mmc_init(struct bd_info *bis)
77 {
78 int rc = 0;
79 (void) bis;
80 #ifdef CONFIG_ARM_PL180_MMCI
81 struct pl180_mmc_host *host;
82 struct mmc *mmc;
83
84 host = malloc(sizeof(struct pl180_mmc_host));
85 if (!host)
86 return -ENOMEM;
87 memset(host, 0, sizeof(*host));
88
89 strcpy(host->name, "MMC");
90 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
91 host->pwr_init = INIT_PWR;
92 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
93 host->voltages = VOLTAGE_WINDOW_MMC;
94 host->caps = 0;
95 host->clock_in = ARM_MCLK;
96 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
97 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
98 rc = arm_pl180_mmci_init(host, &mmc);
99 #endif
100 return rc;
101 }
102
flash__init(void)103 static void flash__init(void)
104 {
105 /* Setup the sytem control register to allow writing to flash */
106 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
107 &sysctrl_base->scflashctrl);
108 }
109
dram_init(void)110 int dram_init(void)
111 {
112 gd->ram_size =
113 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
114 return 0;
115 }
116
dram_init_banksize(void)117 int dram_init_banksize(void)
118 {
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
120 gd->bd->bi_dram[0].size =
121 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
122 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
123 gd->bd->bi_dram[1].size =
124 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
125
126 return 0;
127 }
128
129 /*
130 * Start timer:
131 * Setup a 32 bit timer, running at 1KHz
132 * Versatile Express Motherboard provides 1 MHz timer
133 */
vexpress_timer_init(void)134 static void vexpress_timer_init(void)
135 {
136 /*
137 * Set clock frequency in system controller:
138 * VEXPRESS_REFCLK is 32KHz
139 * VEXPRESS_TIMCLK is 1MHz
140 */
141 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
142 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
143 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
144
145 /*
146 * Set Timer0 to be:
147 * Enabled, free running, no interrupt, 32-bit, wrapping
148 */
149 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
150 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
151 writel(SYSTIMER_EN | SYSTIMER_32BIT |
152 readl(&systimer_base->timer0control),
153 &systimer_base->timer0control);
154 }
155
v2m_cfg_write(u32 devfn,u32 data)156 int v2m_cfg_write(u32 devfn, u32 data)
157 {
158 /* Configuration interface broken? */
159 u32 val;
160
161 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
162
163 val = readl(V2M_SYS_CFGSTAT);
164 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
165
166 writel(data, V2M_SYS_CFGDATA);
167 writel(devfn, V2M_SYS_CFGCTRL);
168
169 do {
170 val = readl(V2M_SYS_CFGSTAT);
171 } while (val == 0);
172
173 return !!(val & SYS_CFG_ERR);
174 }
175
176 /* Use the ARM Watchdog System to cause reset */
reset_cpu(ulong addr)177 void reset_cpu(ulong addr)
178 {
179 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
180 printf("Unable to reboot\n");
181 }
182
lowlevel_init(void)183 void lowlevel_init(void)
184 {
185 }
186
get_board_rev(void)187 ulong get_board_rev(void){
188 return readl((u32 *)SYS_ID);
189 }
190
191 #ifdef CONFIG_ARMV7_NONSEC
192 /* Setting the address at which secondary cores start from.
193 * Versatile Express uses one address for all cores, so ignore corenr
194 */
smp_set_core_boot_addr(unsigned long addr,int corenr)195 void smp_set_core_boot_addr(unsigned long addr, int corenr)
196 {
197 /* The SYSFLAGS register on VExpress needs to be cleared first
198 * by writing to the next address, since any writes to the address
199 * at offset 0 will only be ORed in
200 */
201 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
202 writel(addr, CONFIG_SYSFLAGS_ADDR);
203 }
204 #endif
205