1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * DHCOM DH-iMX6 PDK SPL support
4 *
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-ddr.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/io.h>
22 #include <errno.h>
23 #include <fuse.h>
24 #include <fsl_esdhc_imx.h>
25 #include <i2c.h>
26 #include <mmc.h>
27 #include <spl.h>
28 #include <linux/delay.h>
29
30 #define ENET_PAD_CTRL \
31 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
32 PAD_CTL_HYS)
33
34 #define GPIO_PAD_CTRL \
35 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
36
37 #define SPI_PAD_CTRL \
38 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST)
40
41 #define UART_PAD_CTRL \
42 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45 #define USDHC_PAD_CTRL \
46 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48
49 static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
50 .dram_sdclk_0 = 0x00020030,
51 .dram_sdclk_1 = 0x00020030,
52 .dram_cas = 0x00020030,
53 .dram_ras = 0x00020030,
54 .dram_reset = 0x00020030,
55 .dram_sdcke0 = 0x00003000,
56 .dram_sdcke1 = 0x00003000,
57 .dram_sdba2 = 0x00000000,
58 .dram_sdodt0 = 0x00003030,
59 .dram_sdodt1 = 0x00003030,
60 .dram_sdqs0 = 0x00000030,
61 .dram_sdqs1 = 0x00000030,
62 .dram_sdqs2 = 0x00000030,
63 .dram_sdqs3 = 0x00000030,
64 .dram_sdqs4 = 0x00000030,
65 .dram_sdqs5 = 0x00000030,
66 .dram_sdqs6 = 0x00000030,
67 .dram_sdqs7 = 0x00000030,
68 .dram_dqm0 = 0x00020030,
69 .dram_dqm1 = 0x00020030,
70 .dram_dqm2 = 0x00020030,
71 .dram_dqm3 = 0x00020030,
72 .dram_dqm4 = 0x00020030,
73 .dram_dqm5 = 0x00020030,
74 .dram_dqm6 = 0x00020030,
75 .dram_dqm7 = 0x00020030,
76 };
77
78 static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
79 .grp_ddr_type = 0x000C0000,
80 .grp_ddrmode_ctl = 0x00020000,
81 .grp_ddrpke = 0x00000000,
82 .grp_addds = 0x00000030,
83 .grp_ctlds = 0x00000030,
84 .grp_ddrmode = 0x00020000,
85 .grp_b0ds = 0x00000030,
86 .grp_b1ds = 0x00000030,
87 .grp_b2ds = 0x00000030,
88 .grp_b3ds = 0x00000030,
89 .grp_b4ds = 0x00000030,
90 .grp_b5ds = 0x00000030,
91 .grp_b6ds = 0x00000030,
92 .grp_b7ds = 0x00000030,
93 };
94
95 static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
96 .dram_sdclk_0 = 0x00020030,
97 .dram_sdclk_1 = 0x00020030,
98 .dram_cas = 0x00020030,
99 .dram_ras = 0x00020030,
100 .dram_reset = 0x00020030,
101 .dram_sdcke0 = 0x00003000,
102 .dram_sdcke1 = 0x00003000,
103 .dram_sdba2 = 0x00000000,
104 .dram_sdodt0 = 0x00003030,
105 .dram_sdodt1 = 0x00003030,
106 .dram_sdqs0 = 0x00000030,
107 .dram_sdqs1 = 0x00000030,
108 .dram_sdqs2 = 0x00000030,
109 .dram_sdqs3 = 0x00000030,
110 .dram_sdqs4 = 0x00000030,
111 .dram_sdqs5 = 0x00000030,
112 .dram_sdqs6 = 0x00000030,
113 .dram_sdqs7 = 0x00000030,
114 .dram_dqm0 = 0x00020030,
115 .dram_dqm1 = 0x00020030,
116 .dram_dqm2 = 0x00020030,
117 .dram_dqm3 = 0x00020030,
118 .dram_dqm4 = 0x00020030,
119 .dram_dqm5 = 0x00020030,
120 .dram_dqm6 = 0x00020030,
121 .dram_dqm7 = 0x00020030,
122 };
123
124 static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
125 .grp_ddr_type = 0x000C0000,
126 .grp_ddrmode_ctl = 0x00020000,
127 .grp_ddrpke = 0x00000000,
128 .grp_addds = 0x00000030,
129 .grp_ctlds = 0x00000030,
130 .grp_ddrmode = 0x00020000,
131 .grp_b0ds = 0x00000030,
132 .grp_b1ds = 0x00000030,
133 .grp_b2ds = 0x00000030,
134 .grp_b3ds = 0x00000030,
135 .grp_b4ds = 0x00000030,
136 .grp_b5ds = 0x00000030,
137 .grp_b6ds = 0x00000030,
138 .grp_b7ds = 0x00000030,
139 };
140
141 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
142 .p0_mpwldectrl0 = 0x00150019,
143 .p0_mpwldectrl1 = 0x001C000B,
144 .p1_mpwldectrl0 = 0x00020018,
145 .p1_mpwldectrl1 = 0x0002000C,
146 .p0_mpdgctrl0 = 0x43140320,
147 .p0_mpdgctrl1 = 0x03080304,
148 .p1_mpdgctrl0 = 0x43180320,
149 .p1_mpdgctrl1 = 0x03100254,
150 .p0_mprddlctl = 0x4830383C,
151 .p1_mprddlctl = 0x3836323E,
152 .p0_mpwrdlctl = 0x3E444642,
153 .p1_mpwrdlctl = 0x42344442,
154 };
155
156 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
157 .p0_mpwldectrl0 = 0x0040003C,
158 .p0_mpwldectrl1 = 0x0032003E,
159 .p0_mpdgctrl0 = 0x42350231,
160 .p0_mpdgctrl1 = 0x021A0218,
161 .p0_mprddlctl = 0x4B4B4E49,
162 .p0_mpwrdlctl = 0x3F3F3035,
163 };
164
165 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
166 .p0_mpwldectrl0 = 0x001a001a,
167 .p0_mpwldectrl1 = 0x00260015,
168 .p0_mpdgctrl0 = 0x030c0320,
169 .p0_mpdgctrl1 = 0x03100304,
170 .p0_mprddlctl = 0x432e3538,
171 .p0_mpwrdlctl = 0x363f423d,
172 .p1_mpwldectrl0 = 0x0006001e,
173 .p1_mpwldectrl1 = 0x00050015,
174 .p1_mpdgctrl0 = 0x031c0324,
175 .p1_mpdgctrl1 = 0x030c0258,
176 .p1_mprddlctl = 0x3834313f,
177 .p1_mpwrdlctl = 0x47374a42,
178 };
179
180 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
181 .p0_mpwldectrl0 = 0x003A003A,
182 .p0_mpwldectrl1 = 0x0030002F,
183 .p1_mpwldectrl0 = 0x002F0038,
184 .p1_mpwldectrl1 = 0x00270039,
185 .p0_mpdgctrl0 = 0x420F020F,
186 .p0_mpdgctrl1 = 0x01760175,
187 .p1_mpdgctrl0 = 0x41640171,
188 .p1_mpdgctrl1 = 0x015E0160,
189 .p0_mprddlctl = 0x45464B4A,
190 .p1_mprddlctl = 0x49484A46,
191 .p0_mpwrdlctl = 0x40402E32,
192 .p1_mpwrdlctl = 0x3A3A3231,
193 };
194
195 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
196 .p0_mpwldectrl0 = 0x0040003C,
197 .p0_mpwldectrl1 = 0x0032003E,
198 .p0_mpdgctrl0 = 0x42350231,
199 .p0_mpdgctrl1 = 0x021A0218,
200 .p0_mprddlctl = 0x4B4B4E49,
201 .p0_mpwrdlctl = 0x3F3F3035,
202 };
203
204 /*
205 * 2 Gbit DDR3 memory
206 * - NANYA #NT5CC128M16IP-DII
207 * - NANYA #NT5CB128M16FP-DII
208 */
209 static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
210 .mem_speed = 1600,
211 .density = 2,
212 .width = 16,
213 .banks = 8,
214 .rowaddr = 14,
215 .coladdr = 10,
216 .pagesz = 2,
217 .trcd = 1375,
218 .trcmin = 5863,
219 .trasmin = 3750,
220 };
221
222 /*
223 * 4 Gbit DDR3 memory
224 * - Intelligent Memory #IM4G16D3EABG-125I
225 */
226 static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
227 .mem_speed = 1600,
228 .density = 4,
229 .width = 16,
230 .banks = 8,
231 .rowaddr = 15,
232 .coladdr = 10,
233 .pagesz = 2,
234 .trcd = 1375,
235 .trcmin = 4875,
236 .trasmin = 3500,
237 };
238
239 /* DDR3 64bit */
240 static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
241 /* width of data bus:0=16,1=32,2=64 */
242 .dsize = 2,
243 .cs_density = 32,
244 .ncs = 1, /* single chip select */
245 .cs1_mirror = 1,
246 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
247 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
248 .walat = 1, /* Write additional latency */
249 .ralat = 5, /* Read additional latency */
250 .mif3_mode = 3, /* Command prediction working mode */
251 .bi_on = 1, /* Bank interleaving enabled */
252 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
253 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
254 .refsel = 1, /* Refresh cycles at 32KHz */
255 .refr = 3, /* 4 refresh commands per refresh cycle */
256 };
257
258 /* DDR3 32bit */
259 static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
260 /* width of data bus:0=16,1=32,2=64 */
261 .dsize = 1,
262 .cs_density = 32,
263 .ncs = 1, /* single chip select */
264 .cs1_mirror = 1,
265 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
266 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
267 .walat = 1, /* Write additional latency */
268 .ralat = 5, /* Read additional latency */
269 .mif3_mode = 3, /* Command prediction working mode */
270 .bi_on = 1, /* Bank interleaving enabled */
271 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
272 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
273 .refsel = 1, /* Refresh cycles at 32KHz */
274 .refr = 3, /* 4 refresh commands per refresh cycle */
275 };
276
ccgr_init(void)277 static void ccgr_init(void)
278 {
279 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
280
281 writel(0x00C03F3F, &ccm->CCGR0);
282 writel(0x0030FC03, &ccm->CCGR1);
283 writel(0x0FFFC000, &ccm->CCGR2);
284 writel(0x3FF00000, &ccm->CCGR3);
285 writel(0x00FFF300, &ccm->CCGR4);
286 writel(0x0F0000C3, &ccm->CCGR5);
287 writel(0x000003FF, &ccm->CCGR6);
288 }
289
290 /* Board ID */
291 static iomux_v3_cfg_t const hwcode_pads[] = {
292 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
293 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
294 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
295 };
296
setup_iomux_boardid(void)297 static void setup_iomux_boardid(void)
298 {
299 /* HW code pins: Setup alternate function and configure pads */
300 SETUP_IOMUX_PADS(hwcode_pads);
301 }
302
303 /* DDR Code */
304 static iomux_v3_cfg_t const ddrcode_pads[] = {
305 IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
306 IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
307 };
308
setup_iomux_ddrcode(void)309 static void setup_iomux_ddrcode(void)
310 {
311 /* ddr code pins */
312 SETUP_IOMUX_PADS(ddrcode_pads);
313 }
314
315 enum dhcom_ddr3_code {
316 DH_DDR3_SIZE_256MIB = 0x00,
317 DH_DDR3_SIZE_512MIB = 0x01,
318 DH_DDR3_SIZE_1GIB = 0x02,
319 DH_DDR3_SIZE_2GIB = 0x03
320 };
321
322 #define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
323 #define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
324
dhcom_get_ddr3_code(void)325 enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
326 {
327 enum dhcom_ddr3_code ddr3_code;
328
329 gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
330 gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
331
332 gpio_direction_input(DDR3_CODE_BIT_0);
333 gpio_direction_input(DDR3_CODE_BIT_1);
334
335 /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
336 ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
337 | (!!gpio_get_value(DDR3_CODE_BIT_0));
338
339 return ddr3_code;
340 }
341
342 /* GPIO */
343 static iomux_v3_cfg_t const gpio_pads[] = {
344 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
345 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
346 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
347 IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
348 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
349 IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
350 IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
351 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
352 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
353 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
354 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
355 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
356 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
357 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
358 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
359 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
360 IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
361 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
362 IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
363 IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
364 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
365 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
366 IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
367 };
368
setup_iomux_gpio(void)369 static void setup_iomux_gpio(void)
370 {
371 SETUP_IOMUX_PADS(gpio_pads);
372 }
373
374 /* Ethernet */
375 static iomux_v3_cfg_t const enet_pads[] = {
376 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
377 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
378 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
379 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
380 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
381 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
382 IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
383 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
384 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
385 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
386 /* SMSC PHY Reset */
387 IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
388 /* ENET_VIO_GPIO */
389 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
390 /* ENET_Interrupt - (not used) */
391 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
392 };
393
setup_iomux_enet(void)394 static void setup_iomux_enet(void)
395 {
396 SETUP_IOMUX_PADS(enet_pads);
397 }
398
399 /* SD interface */
400 static iomux_v3_cfg_t const usdhc2_pads[] = {
401 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
402 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
403 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
404 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
405 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
406 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
407 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
408 };
409
410 /* onboard microSD */
411 static iomux_v3_cfg_t const usdhc3_pads[] = {
412 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
413 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
414 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
415 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
416 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
417 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
418 IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
419 };
420
421 /* eMMC */
422 static iomux_v3_cfg_t const usdhc4_pads[] = {
423 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
424 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
425 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
426 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
427 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
428 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
429 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
430 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
431 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
432 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
433 };
434
435 /* SD */
setup_iomux_sd(void)436 static void setup_iomux_sd(void)
437 {
438 SETUP_IOMUX_PADS(usdhc2_pads);
439 SETUP_IOMUX_PADS(usdhc3_pads);
440 SETUP_IOMUX_PADS(usdhc4_pads);
441 }
442
443 /* SPI */
444 static iomux_v3_cfg_t const ecspi1_pads[] = {
445 /* SS0 - SS of boot flash */
446 IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
447 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
448 /* SS2 - SS of DHCOM SPI1 */
449 IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
450 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
451
452 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
453 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
454 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
455 };
456
setup_iomux_spi(void)457 static void setup_iomux_spi(void)
458 {
459 SETUP_IOMUX_PADS(ecspi1_pads);
460 }
461
board_spi_cs_gpio(unsigned bus,unsigned cs)462 int board_spi_cs_gpio(unsigned bus, unsigned cs)
463 {
464 if (bus == 0 && cs == 0)
465 return IMX_GPIO_NR(2, 30);
466 else
467 return -1;
468 }
469
470 /* UART */
471 static iomux_v3_cfg_t const uart1_pads[] = {
472 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
473 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
474 };
475
setup_iomux_uart(void)476 static void setup_iomux_uart(void)
477 {
478 SETUP_IOMUX_PADS(uart1_pads);
479 }
480
481 #ifdef CONFIG_FSL_USDHC
482 struct fsl_esdhc_cfg usdhc_cfg[1] = {
483 {USDHC4_BASE_ADDR},
484 };
485
board_mmc_get_env_dev(int devno)486 int board_mmc_get_env_dev(int devno)
487 {
488 return devno - 1;
489 }
490
board_mmc_getcd(struct mmc * mmc)491 int board_mmc_getcd(struct mmc *mmc)
492 {
493 return 1; /* eMMC/uSDHC4 is always present */
494 }
495
board_mmc_init(struct bd_info * bis)496 int board_mmc_init(struct bd_info *bis)
497 {
498 SETUP_IOMUX_PADS(usdhc4_pads);
499 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
500 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
501 usdhc_cfg[0].max_bus_width = 8;
502
503 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
504 }
505 #endif
506
507 /* USB */
508 static iomux_v3_cfg_t const usb_pads[] = {
509 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
510 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
511 };
512
setup_iomux_usb(void)513 static void setup_iomux_usb(void)
514 {
515 SETUP_IOMUX_PADS(usb_pads);
516 }
517
518 /* Perform DDR DRAM calibration */
spl_dram_perform_cal(struct mx6_ddr_sysinfo const * sysinfo)519 static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
520 {
521 int ret = 0;
522
523 #ifdef CONFIG_MX6_DDRCAL
524 udelay(100);
525 ret = mmdc_do_write_level_calibration(sysinfo);
526 if (ret) {
527 printf("DDR3: Write level calibration error [%d]\n", ret);
528 return ret;
529 }
530
531 ret = mmdc_do_dqs_calibration(sysinfo);
532 if (ret) {
533 printf("DDR3: DQS calibration error [%d]\n", ret);
534 return ret;
535 }
536 #endif /* CONFIG_MX6_DDRCAL */
537
538 return ret;
539 }
540
541
542 /* DRAM */
dhcom_spl_dram_init(void)543 static void dhcom_spl_dram_init(void)
544 {
545 enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
546
547 if (is_mx6dq()) {
548 mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
549 &dhcom6dq_grp_ioregs);
550 switch (ddr3_code) {
551 default:
552 printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
553 printf(" choosing 1024 MB\n");
554 /* fall through */
555 case DH_DDR3_SIZE_1GIB:
556 mx6_dram_cfg(&dhcom_ddr_64bit,
557 &dhcom_mmdc_calib_4x2g_1066,
558 &dhcom_mem_ddr_2g);
559 break;
560 case DH_DDR3_SIZE_2GIB:
561 mx6_dram_cfg(&dhcom_ddr_64bit,
562 &dhcom_mmdc_calib_4x4g_1066,
563 &dhcom_mem_ddr_4g);
564 break;
565 }
566
567 /* Perform DDR DRAM calibration */
568 spl_dram_perform_cal(&dhcom_ddr_64bit);
569
570 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
571 mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
572 &dhcom6sdl_grp_ioregs);
573 switch (ddr3_code) {
574 default:
575 printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
576 printf(" choosing 1024 MB\n");
577 /* fall through */
578 case DH_DDR3_SIZE_1GIB:
579 mx6_dram_cfg(&dhcom_ddr_64bit,
580 &dhcom_mmdc_calib_4x2g_800,
581 &dhcom_mem_ddr_2g);
582 break;
583 }
584
585 /* Perform DDR DRAM calibration */
586 spl_dram_perform_cal(&dhcom_ddr_64bit);
587
588 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
589 mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
590 &dhcom6sdl_grp_ioregs);
591 switch (ddr3_code) {
592 default:
593 printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
594 printf(" choosing 512 MB\n");
595 /* fall through */
596 case DH_DDR3_SIZE_512MIB:
597 mx6_dram_cfg(&dhcom_ddr_32bit,
598 &dhcom_mmdc_calib_2x2g_800,
599 &dhcom_mem_ddr_2g);
600 break;
601 case DH_DDR3_SIZE_1GIB:
602 mx6_dram_cfg(&dhcom_ddr_32bit,
603 &dhcom_mmdc_calib_2x4g_800,
604 &dhcom_mem_ddr_4g);
605 break;
606 }
607
608 /* Perform DDR DRAM calibration */
609 spl_dram_perform_cal(&dhcom_ddr_32bit);
610 }
611 }
612
board_init_f(ulong dummy)613 void board_init_f(ulong dummy)
614 {
615 /* setup AIPS and disable watchdog */
616 arch_cpu_init();
617
618 ccgr_init();
619 gpr_init();
620
621 /* setup GP timer */
622 timer_init();
623
624 setup_iomux_boardid();
625 setup_iomux_ddrcode();
626 setup_iomux_gpio();
627 setup_iomux_enet();
628 setup_iomux_sd();
629 setup_iomux_spi();
630 setup_iomux_uart();
631 setup_iomux_usb();
632
633 /* UART clocks enabled and gd valid - init serial console */
634 preloader_console_init();
635
636 /* DDR3 initialization */
637 dhcom_spl_dram_init();
638
639 /* Clear the BSS. */
640 memset(__bss_start, 0, __bss_end - __bss_start);
641
642 /* load/boot image from boot device */
643 board_init_r(NULL, 0);
644 }
645