1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
4 *
5 * Based on other i.MX6 boards
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <net.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <env.h>
16 #include <asm/global_data.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/iomux-v3.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <asm/mach-imx/video.h>
24 #include <mmc.h>
25 #include <fsl_esdhc_imx.h>
26 #include <miiphy.h>
27 #include <netdev.h>
28 #include <asm/arch/mxc_hdmi.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/io.h>
31 #include <asm/arch/sys_proto.h>
32 #include <i2c.h>
33 #include <input.h>
34 #include <power/pmic.h>
35 #include <power/pfuze100_pmic.h>
36 #include <asm/arch/mx6-ddr.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
41
42 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
52
53 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
55
56 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
58
59 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
61
62 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
64 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
65
66 #define I2C_PMIC 1
67
68 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
69
70 #define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
71
dram_init(void)72 int dram_init(void)
73 {
74 gd->ram_size = imx_ddr_size();
75
76 return 0;
77 }
78
79 iomux_v3_cfg_t const uart2_pads[] = {
80 MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81 MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 };
83
setup_iomux_uart(void)84 static void setup_iomux_uart(void)
85 {
86 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
87 }
88
89 #ifdef CONFIG_TARGET_ZC5202
90 iomux_v3_cfg_t const enet_pads[] = {
91 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
98 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
105 /* Switch Reset */
106 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
107 /* Switch Interrupt */
108 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
109 /* use CRS and COL pads as GPIOs */
110 MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
111 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
112
113 };
114
115 #define BOARD_NAME "EL6x-ZC5202"
116 #else
117 iomux_v3_cfg_t const enet_pads[] = {
118 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
127 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
131 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
132 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
133 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
134 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
135 };
136 #define BOARD_NAME "EL6x-ZC5601"
137 #endif
138
setup_iomux_enet(void)139 static void setup_iomux_enet(void)
140 {
141 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
142
143 #ifdef CONFIG_TARGET_ZC5202
144 /* set CRS and COL to input */
145 gpio_direction_input(IMX_GPIO_NR(4, 9));
146 gpio_direction_input(IMX_GPIO_NR(4, 12));
147
148 /* Reset Switch */
149 gpio_direction_output(ETH_PHY_RESET , 0);
150 mdelay(2);
151 gpio_set_value(ETH_PHY_RESET, 1);
152 #endif
153 }
154
board_phy_config(struct phy_device * phydev)155 int board_phy_config(struct phy_device *phydev)
156 {
157 if (phydev->drv->config)
158 phydev->drv->config(phydev);
159
160 return 0;
161 }
162
163 #ifdef CONFIG_MXC_SPI
164 #ifdef CONFIG_TARGET_ZC5202
165 iomux_v3_cfg_t const ecspi1_pads[] = {
166 MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
167 MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
168 MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
169 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 };
172
173 iomux_v3_cfg_t const ecspi3_pads[] = {
174 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
175 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
176 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
177 MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL),
178 MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL),
179 MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
180 MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL),
181 };
182 #endif
183
184 iomux_v3_cfg_t const ecspi4_pads[] = {
185 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
186 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
187 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
188 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
189 };
190
board_spi_cs_gpio(unsigned bus,unsigned cs)191 int board_spi_cs_gpio(unsigned bus, unsigned cs)
192 {
193 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
194 ? (IMX_GPIO_NR(3, 20)) : -1;
195 }
196
setup_spi(void)197 static void setup_spi(void)
198 {
199 #ifdef CONFIG_TARGET_ZC5202
200 gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
201 gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
202 gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
203 gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
204 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
205 #endif
206
207 gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
208 gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
209 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
210
211 enable_spi_clk(true, 3);
212 }
213 #endif
214
215 static struct i2c_pads_info i2c_pad_info1 = {
216 .scl = {
217 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
218 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
219 .gp = IMX_GPIO_NR(2, 30)
220 },
221 .sda = {
222 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
223 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
224 .gp = IMX_GPIO_NR(4, 13)
225 }
226 };
227
228 static struct i2c_pads_info i2c_pad_info2 = {
229 .scl = {
230 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
231 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
232 .gp = IMX_GPIO_NR(1, 5)
233 },
234 .sda = {
235 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
236 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
237 .gp = IMX_GPIO_NR(7, 11)
238 }
239 };
240
241 iomux_v3_cfg_t const usdhc2_pads[] = {
242 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
243 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
244 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
245 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
246 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
247 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
248 MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
249 };
250
251 iomux_v3_cfg_t const usdhc4_pads[] = {
252 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
261 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
262 };
263
264 #ifdef CONFIG_FSL_ESDHC_IMX
265 struct fsl_esdhc_cfg usdhc_cfg[2] = {
266 {USDHC2_BASE_ADDR},
267 {USDHC4_BASE_ADDR},
268 };
269
270 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
271
board_mmc_getcd(struct mmc * mmc)272 int board_mmc_getcd(struct mmc *mmc)
273 {
274 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
275 int ret = 0;
276
277 switch (cfg->esdhc_base) {
278 case USDHC2_BASE_ADDR:
279 ret = !gpio_get_value(USDHC2_CD_GPIO);
280 break;
281 case USDHC4_BASE_ADDR:
282 ret = 1; /* eMMC/uSDHC4 is always present */
283 break;
284 }
285
286 return ret;
287 }
288
board_mmc_init(struct bd_info * bis)289 int board_mmc_init(struct bd_info *bis)
290 {
291 #ifndef CONFIG_SPL_BUILD
292 int ret;
293 int i;
294
295 /*
296 * According to the board_mmc_init() the following map is done:
297 * (U-boot device node) (Physical Port)
298 * mmc0 SD2
299 * mmc1 SD3
300 * mmc2 eMMC
301 */
302 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
303 switch (i) {
304 case 0:
305 imx_iomux_v3_setup_multiple_pads(
306 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
307 gpio_direction_input(USDHC2_CD_GPIO);
308 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
309 break;
310 case 1:
311 imx_iomux_v3_setup_multiple_pads(
312 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
313 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
314 break;
315 default:
316 printf("Warning: you configured more USDHC controllers"
317 "(%d) then supported by the board (%d)\n",
318 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
319 return -EINVAL;
320 }
321
322 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
323 if (ret)
324 return ret;
325 }
326
327 return 0;
328 #else
329 struct src *psrc = (struct src *)SRC_BASE_ADDR;
330 unsigned reg = readl(&psrc->sbmr1) >> 11;
331
332 /*
333 * Upon reading BOOT_CFG register the following map is done:
334 * Bit 11 and 12 of BOOT_CFG register can determine the current
335 * mmc port
336 * 0x1 SD1
337 * 0x2 SD2
338 * 0x3 SD4
339 */
340
341 switch (reg & 0x3) {
342 case 0x1:
343 imx_iomux_v3_setup_multiple_pads(
344 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
345 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
346 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
347 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
348 break;
349 case 0x3:
350 imx_iomux_v3_setup_multiple_pads(
351 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
352 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
353 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
354 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
355 break;
356 }
357
358 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
359 #endif
360
361 }
362 #endif
363
364
365 /*
366 * Do not overwrite the console
367 * Use always serial for U-Boot console
368 */
overwrite_console(void)369 int overwrite_console(void)
370 {
371 return 1;
372 }
373
board_eth_init(struct bd_info * bis)374 int board_eth_init(struct bd_info *bis)
375 {
376 setup_iomux_enet();
377 enable_enet_clk(1);
378
379 return cpu_eth_init(bis);
380 }
381
board_early_init_f(void)382 int board_early_init_f(void)
383 {
384
385 setup_iomux_uart();
386 setup_spi();
387
388 return 0;
389 }
390
board_init(void)391 int board_init(void)
392 {
393 /* address of boot parameters */
394 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
395
396 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
397 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
398
399 return 0;
400 }
401
power_init_board(void)402 int power_init_board(void)
403 {
404 struct pmic *p;
405 int ret;
406 unsigned int reg;
407
408 ret = power_pfuze100_init(I2C_PMIC);
409 if (ret)
410 return ret;
411
412 p = pmic_get("PFUZE100");
413 ret = pmic_probe(p);
414 if (ret)
415 return ret;
416
417 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
418 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
419
420 /* Increase VGEN3 from 2.5 to 2.8V */
421 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
422 reg &= ~LDO_VOL_MASK;
423 reg |= LDOB_2_80V;
424 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
425
426 /* Increase VGEN5 from 2.8 to 3V */
427 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
428 reg &= ~LDO_VOL_MASK;
429 reg |= LDOB_3_00V;
430 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
431
432 /* Set SW1AB stanby volage to 0.975V */
433 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
434 reg &= ~SW1x_STBY_MASK;
435 reg |= SW1x_0_975V;
436 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
437
438 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
439 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
440 reg &= ~SW1xCONF_DVSSPEED_MASK;
441 reg |= SW1xCONF_DVSSPEED_4US;
442 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
443
444 /* Set SW1C standby voltage to 0.975V */
445 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
446 reg &= ~SW1x_STBY_MASK;
447 reg |= SW1x_0_975V;
448 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
449
450 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
451 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
452 reg &= ~SW1xCONF_DVSSPEED_MASK;
453 reg |= SW1xCONF_DVSSPEED_4US;
454 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
455
456 return 0;
457 }
458
459 #ifdef CONFIG_CMD_BMODE
460 static const struct boot_mode board_boot_modes[] = {
461 /* 4 bit bus width */
462 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
463 /* 8 bit bus width */
464 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
465 {NULL, 0},
466 };
467 #endif
468
board_late_init(void)469 int board_late_init(void)
470 {
471 #ifdef CONFIG_CMD_BMODE
472 add_board_boot_modes(board_boot_modes);
473 #endif
474
475 env_set("board_name", BOARD_NAME);
476 return 0;
477 }
478
checkboard(void)479 int checkboard(void)
480 {
481 puts("Board: ");
482 puts(BOARD_NAME "\n");
483
484 return 0;
485 }
486
487 #ifdef CONFIG_SPL_BUILD
488 #include <spl.h>
489 #include <linux/libfdt.h>
490
491 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
492 .dram_sdclk_0 = 0x00020030,
493 .dram_sdclk_1 = 0x00020030,
494 .dram_cas = 0x00020030,
495 .dram_ras = 0x00020030,
496 .dram_reset = 0x00020030,
497 .dram_sdcke0 = 0x00003000,
498 .dram_sdcke1 = 0x00003000,
499 .dram_sdba2 = 0x00000000,
500 .dram_sdodt0 = 0x00003030,
501 .dram_sdodt1 = 0x00003030,
502 .dram_sdqs0 = 0x00000030,
503 .dram_sdqs1 = 0x00000030,
504 .dram_sdqs2 = 0x00000030,
505 .dram_sdqs3 = 0x00000030,
506 .dram_sdqs4 = 0x00000030,
507 .dram_sdqs5 = 0x00000030,
508 .dram_sdqs6 = 0x00000030,
509 .dram_sdqs7 = 0x00000030,
510 .dram_dqm0 = 0x00020030,
511 .dram_dqm1 = 0x00020030,
512 .dram_dqm2 = 0x00020030,
513 .dram_dqm3 = 0x00020030,
514 .dram_dqm4 = 0x00020030,
515 .dram_dqm5 = 0x00020030,
516 .dram_dqm6 = 0x00020030,
517 .dram_dqm7 = 0x00020030,
518 };
519
520 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
521 .grp_ddr_type = 0x000C0000,
522 .grp_ddrmode_ctl = 0x00020000,
523 .grp_ddrpke = 0x00000000,
524 .grp_addds = 0x00000030,
525 .grp_ctlds = 0x00000030,
526 .grp_ddrmode = 0x00020000,
527 .grp_b0ds = 0x00000030,
528 .grp_b1ds = 0x00000030,
529 .grp_b2ds = 0x00000030,
530 .grp_b3ds = 0x00000030,
531 .grp_b4ds = 0x00000030,
532 .grp_b5ds = 0x00000030,
533 .grp_b6ds = 0x00000030,
534 .grp_b7ds = 0x00000030,
535 };
536
537 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
538 .p0_mpwldectrl0 = 0x001F001F,
539 .p0_mpwldectrl1 = 0x001F001F,
540 .p1_mpwldectrl0 = 0x00440044,
541 .p1_mpwldectrl1 = 0x00440044,
542 .p0_mpdgctrl0 = 0x434B0350,
543 .p0_mpdgctrl1 = 0x034C0359,
544 .p1_mpdgctrl0 = 0x434B0350,
545 .p1_mpdgctrl1 = 0x03650348,
546 .p0_mprddlctl = 0x4436383B,
547 .p1_mprddlctl = 0x39393341,
548 .p0_mpwrdlctl = 0x35373933,
549 .p1_mpwrdlctl = 0x48254A36,
550 };
551
552 /* MT41K128M16JT-125 */
553 static struct mx6_ddr3_cfg mem_ddr = {
554 .mem_speed = 1600,
555 .density = 2,
556 .width = 16,
557 .banks = 8,
558 .rowaddr = 14,
559 .coladdr = 10,
560 .pagesz = 2,
561 .trcd = 1375,
562 .trcmin = 4875,
563 .trasmin = 3500,
564 };
565
ccgr_init(void)566 static void ccgr_init(void)
567 {
568 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
569
570 writel(0x00C03F3F, &ccm->CCGR0);
571 writel(0x0030FC03, &ccm->CCGR1);
572 writel(0x0FFFC000, &ccm->CCGR2);
573 writel(0x3FF00000, &ccm->CCGR3);
574 writel(0x00FFF300, &ccm->CCGR4);
575 writel(0x0F0000C3, &ccm->CCGR5);
576 writel(0x000003FF, &ccm->CCGR6);
577 }
578
579 /*
580 * This section requires the differentiation between iMX6 Sabre boards, but
581 * for now, it will configure only for the mx6q variant.
582 */
spl_dram_init(void)583 static void spl_dram_init(void)
584 {
585 struct mx6_ddr_sysinfo sysinfo = {
586 /* width of data bus:0=16,1=32,2=64 */
587 .dsize = 2,
588 /* config for full 4GB range so that get_mem_size() works */
589 .cs_density = 32, /* 32Gb per CS */
590 /* single chip select */
591 .ncs = 1,
592 .cs1_mirror = 0,
593 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
594 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
595 .walat = 1, /* Write additional latency */
596 .ralat = 5, /* Read additional latency */
597 .mif3_mode = 3, /* Command prediction working mode */
598 .bi_on = 1, /* Bank interleaving enabled */
599 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
600 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
601 .ddr_type = DDR_TYPE_DDR3,
602 .refsel = 1, /* Refresh cycles at 32KHz */
603 .refr = 7, /* 8 refresh commands per refresh cycle */
604 };
605
606 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
607 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
608 }
609
board_init_f(ulong dummy)610 void board_init_f(ulong dummy)
611 {
612 /* setup AIPS and disable watchdog */
613 arch_cpu_init();
614
615 ccgr_init();
616 gpr_init();
617
618 /* iomux and setup of i2c */
619 board_early_init_f();
620
621 /* setup GP timer */
622 timer_init();
623
624 /* UART clocks enabled and gd valid - init serial console */
625 preloader_console_init();
626
627 /* DDR initialization */
628 spl_dram_init();
629
630 /* Clear the BSS. */
631 memset(__bss_start, 0, __bss_end - __bss_start);
632
633 /* load/boot image from boot device */
634 board_init_r(NULL, 0);
635 }
636
637 #endif
638