1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C)Copyright 2016 Rockchip Electronics Co., Ltd
4 * Authors: Andy Yan <andy.yan@rock-chips.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <syscon.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/grf_rv1108.h>
14 #include <asm/arch-rockchip/hardware.h>
15 #include <asm/gpio.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
board_early_init_f(void)19 int board_early_init_f(void)
20 {
21 struct rv1108_grf *grf;
22 enum {
23 GPIO3C3_SHIFT = 6,
24 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
25
26 GPIO3C2_SHIFT = 4,
27 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
28
29 GPIO2D2_SHIFT = 4,
30 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
31 GPIO2D2_GPIO = 0,
32 GPIO2D2_UART2_SOUT_M0,
33
34 GPIO2D1_SHIFT = 2,
35 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
36 GPIO2D1_GPIO = 0,
37 GPIO2D1_UART2_SIN_M0,
38 };
39
40 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
41
42 /* Elgin board use UART2 m0 for debug*/
43 rk_clrsetreg(&grf->gpio2d_iomux,
44 GPIO2D2_MASK | GPIO2D1_MASK,
45 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
46 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
47 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
48
49 return 0;
50 }
51
52 #define MODEM_ENABLE_GPIO 111
53
rk_board_late_init(void)54 int rk_board_late_init(void)
55 {
56 gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
57 gpio_direction_output(MODEM_ENABLE_GPIO, 0);
58
59 return 0;
60 }
61
dram_init(void)62 int dram_init(void)
63 {
64 gd->ram_size = 0x8000000;
65
66 return 0;
67 }
68
dram_init_banksize(void)69 int dram_init_banksize(void)
70 {
71 gd->bd->bi_dram[0].start = 0x60000000;
72 gd->bd->bi_dram[0].size = 0x8000000;
73
74 return 0;
75 }
76