1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 */
7
8 #include <common.h>
9 #include <clock_legacy.h>
10 #include <fdt_support.h>
11 #include <init.h>
12 #if defined(CONFIG_OF_LIBFDT)
13 #include <linux/libfdt.h>
14 #endif
15 #include <pci.h>
16 #include <mpc83xx.h>
17 #include <vsc7385.h>
18 #include <ns16550.h>
19 #include <nand.h>
20 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
21 #include <asm/gpio.h>
22 #endif
23 #include <asm/global_data.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
board_early_init_f(void)27 int board_early_init_f(void)
28 {
29 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
30 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
31
32 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
33 gd->flags |= GD_FLG_SILENT;
34 #endif
35 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
36 mpc83xx_gpio_init_f();
37 #endif
38
39 return 0;
40 }
41
board_early_init_r(void)42 int board_early_init_r(void)
43 {
44 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
45 mpc83xx_gpio_init_r();
46 #endif
47
48 return 0;
49 }
50
checkboard(void)51 int checkboard(void)
52 {
53 puts("Board: Freescale MPC8313ERDB\n");
54 return 0;
55 }
56
57 #ifndef CONFIG_SPL_BUILD
58 static struct pci_region pci_regions[] = {
59 {
60 .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
61 .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
62 .size = CONFIG_SYS_PCI1_MEM_SIZE,
63 .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
64 },
65 {
66 .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
67 .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
68 .size = CONFIG_SYS_PCI1_MMIO_SIZE,
69 .flags = PCI_REGION_MEM
70 },
71 {
72 .bus_start = CONFIG_SYS_PCI1_IO_BASE,
73 .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
74 .size = CONFIG_SYS_PCI1_IO_SIZE,
75 .flags = PCI_REGION_IO
76 }
77 };
78
pci_init_board(void)79 void pci_init_board(void)
80 {
81 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
82 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
83 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
84 struct pci_region *reg[] = { pci_regions };
85
86 /* Enable all 3 PCI_CLK_OUTPUTs. */
87 clk->occr |= 0xe0000000;
88
89 /*
90 * Configure PCI Local Access Windows
91 */
92 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
93 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
94
95 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
96 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
97
98 mpc83xx_pci_init(1, reg);
99 }
100
101 /*
102 * Miscellaneous late-boot configurations
103 *
104 * If a VSC7385 microcode image is present, then upload it.
105 */
misc_init_r(void)106 int misc_init_r(void)
107 {
108 int rc = 0;
109
110 #ifdef CONFIG_VSC7385_IMAGE
111 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
112 CONFIG_VSC7385_IMAGE_SIZE)) {
113 puts("Failure uploading VSC7385 microcode.\n");
114 rc = 1;
115 }
116 #endif
117
118 return rc;
119 }
120
121 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)122 int ft_board_setup(void *blob, struct bd_info *bd)
123 {
124 ft_cpu_setup(blob, bd);
125 #ifdef CONFIG_PCI
126 ft_pci_setup(blob, bd);
127 #endif
128
129 return 0;
130 }
131 #endif
132 #else /* CONFIG_SPL_BUILD */
board_init_f(ulong bootflag)133 void board_init_f(ulong bootflag)
134 {
135 board_early_init_f();
136 ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
137 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
138 puts("NAND boot... ");
139 timer_init();
140 dram_init();
141 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
142 CONFIG_SYS_NAND_U_BOOT_RELOC);
143 }
144
board_init_r(gd_t * gd,ulong dest_addr)145 void board_init_r(gd_t *gd, ulong dest_addr)
146 {
147 nand_boot();
148 }
149
putc(char c)150 void putc(char c)
151 {
152 if (gd->flags & GD_FLG_SILENT)
153 return;
154
155 if (c == '\n')
156 ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
157
158 ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
159 }
160 #endif
161