1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
4  *
5  * Authors: Nick.Spence@freescale.com
6  *          Wilson.Lo@freescale.com
7  *          scottwood@freescale.com
8  */
9 
10 #include <common.h>
11 #include <init.h>
12 #include <mpc83xx.h>
13 #include <spd_sdram.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 
17 #include <asm/bitops.h>
18 #include <asm/io.h>
19 
20 #include <asm/processor.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
resume_from_sleep(void)24 static void resume_from_sleep(void)
25 {
26 	u32 magic = *(u32 *)0;
27 
28 	typedef void (*func_t)(void);
29 	func_t resume = *(func_t *)4;
30 
31 	if (magic == 0xf5153ae5)
32 		resume();
33 
34 	gd->flags &= ~GD_FLG_SILENT;
35 	puts("\nResume from sleep failed: bad magic word\n");
36 }
37 
38 /* Fixed sdram init -- doesn't use serial presence detect.
39  *
40  * This is useful for faster booting in configs where the RAM is unlikely
41  * to be changed, or for things like NAND booting where space is tight.
42  */
43 #ifndef CONFIG_SYS_RAMBOOT
fixed_sdram(void)44 static long fixed_sdram(void)
45 {
46 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
47 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
48 	u32 msize_log2 = __ilog2(msize);
49 
50 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
51 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
52 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
53 
54 	/*
55 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
56 	 * or the DDR2 controller may fail to initialize correctly.
57 	 */
58 	__udelay(50000);
59 
60 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
61 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
62 
63 	/* Currently we use only one CS, so disable the other bank. */
64 	im->ddr.cs_config[1] = 0;
65 
66 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
67 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
68 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
69 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
70 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
71 
72 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
73 		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
74 	else
75 		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
76 
77 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
78 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
79 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
80 
81 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
82 	sync();
83 
84 	/* enable DDR controller */
85 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
86 	sync();
87 
88 	return msize;
89 }
90 #else
fixed_sdram(void)91 static long fixed_sdram(void)
92 {
93 	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
94 }
95 #endif /* CONFIG_SYS_RAMBOOT */
96 
dram_init(void)97 int dram_init(void)
98 {
99 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
100 	u32 msize;
101 
102 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
103 		return -ENXIO;
104 
105 	/* DDR SDRAM */
106 	msize = fixed_sdram();
107 
108 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
109 		resume_from_sleep();
110 
111 	/* set total bus SDRAM size(bytes)  -- DDR */
112 	gd->ram_size = msize;
113 
114 	return 0;
115 }
116