1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 */
5
6 #include <common.h>
7 #include <fdt_support.h>
8 #include <init.h>
9 #include <ioports.h>
10 #include <log.h>
11 #include <mpc83xx.h>
12 #include <i2c.h>
13 #include <miiphy.h>
14 #include <vsc7385.h>
15 #ifdef CONFIG_PCI
16 #include <asm/mpc8349_pci.h>
17 #include <pci.h>
18 #endif
19 #include <spd_sdram.h>
20 #include <asm/bitops.h>
21 #include <asm/global_data.h>
22 #include <asm/mmu.h>
23 #if defined(CONFIG_OF_LIBFDT)
24 #include <linux/libfdt.h>
25 #endif
26 #include <linux/delay.h>
27
28 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
29 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #ifndef CONFIG_SPD_EEPROM
34 /*************************************************************************
35 * fixed sdram init -- doesn't use serial presence detect.
36 ************************************************************************/
fixed_sdram(void)37 int fixed_sdram(void)
38 {
39 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
40 /* The size of RAM, in bytes */
41 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
42 u32 ddr_size_log2 = __ilog2(ddr_size);
43
44 im->sysconf.ddrlaw[0].ar =
45 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
46 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
47
48 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
49 #warning Chip select bounds is only configurable in 16MB increments
50 #endif
51 im->ddr.csbnds[0].csbnds =
52 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
53 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
54 CSBNDS_EA_SHIFT) & CSBNDS_EA);
55 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
56
57 /* Only one CS for DDR */
58 im->ddr.cs_config[1] = 0;
59 im->ddr.cs_config[2] = 0;
60 im->ddr.cs_config[3] = 0;
61
62 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
63 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
64
65 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
66 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
67
68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
69 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
70 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
71 im->ddr.sdram_mode =
72 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
73 im->ddr.sdram_interval =
74 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
75 SDRAM_INTERVAL_BSTOPRE_SHIFT);
76 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
77
78 udelay(200);
79
80 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
81
82 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
83 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
84 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
85 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
86 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
87
88 return CONFIG_SYS_DDR_SIZE;
89 }
90 #endif
91
92 #ifdef CONFIG_PCI
93 /*
94 * Initialize PCI Devices, report devices found
95 */
96 #ifndef CONFIG_PCI_PNP
97 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
98 {
99 PCI_ANY_ID,
100 PCI_ANY_ID,
101 PCI_ANY_ID,
102 PCI_ANY_ID,
103 0x0f,
104 PCI_ANY_ID,
105 pci_cfgfunc_config_device,
106 {
107 PCI_ENET0_IOADDR,
108 PCI_ENET0_MEMADDR,
109 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
110 },
111 {}
112 }
113 #endif
114
115 volatile static struct pci_controller hose[] = {
116 {
117 #ifndef CONFIG_PCI_PNP
118 config_table:pci_mpc83xxmitx_config_table,
119 #endif
120 },
121 {
122 #ifndef CONFIG_PCI_PNP
123 config_table:pci_mpc83xxmitx_config_table,
124 #endif
125 }
126 };
127 #endif /* CONFIG_PCI */
128
dram_init(void)129 int dram_init(void)
130 {
131 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
132 u32 msize = 0;
133 #ifdef CONFIG_DDR_ECC
134 volatile ddr83xx_t *ddr = &im->ddr;
135 #endif
136
137 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
138 return -ENXIO;
139
140 /* DDR SDRAM - Main SODIMM */
141 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
142 #ifdef CONFIG_SPD_EEPROM
143 msize = spd_sdram();
144 #else
145 msize = fixed_sdram();
146 #endif
147
148 #ifdef CONFIG_DDR_ECC
149 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
150 /* Unlike every other board, on the 83xx spd_sdram() returns
151 megabytes instead of just bytes. That's why we need to
152 multiple by 1MB when calling ddr_enable_ecc(). */
153 ddr_enable_ecc(msize * 1048576);
154 #endif
155
156 /* return total bus RAM size(bytes) */
157 gd->ram_size = msize * 1024 * 1024;
158
159 return 0;
160 }
161
checkboard(void)162 int checkboard(void)
163 {
164 #ifdef CONFIG_TARGET_MPC8349ITX
165 puts("Board: Freescale MPC8349E-mITX\n");
166 #else
167 puts("Board: Freescale MPC8349E-mITX-GP\n");
168 #endif
169
170 return 0;
171 }
172
173 /*
174 * Implement a work-around for a hardware problem with compact
175 * flash.
176 *
177 * Program the UPM if compact flash is enabled.
178 */
misc_init_f(void)179 int misc_init_f(void)
180 {
181 #ifdef CONFIG_VSC7385_ENET
182 volatile u32 *vsc7385_cpuctrl;
183
184 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
185 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
186 means it is 0 when the IRQ is not active. This makes the wire-AND
187 logic always assert IRQ7 to CPU even if there is no request from the
188 switch. Since the compact flash and the switch share the same IRQ,
189 the Linux kernel will think that the compact flash is requesting irq
190 and get stuck when it tries to clear the IRQ. Thus we need to set
191 the L2_IRQ0 and L2_IRQ1 to active low.
192
193 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
194 Without this code, compact flash will not work in Linux because
195 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
196 don't enable compact flash for U-Boot.
197 */
198
199 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
200 *vsc7385_cpuctrl |= 0x0c;
201 #endif
202
203 #ifdef CONFIG_COMPACT_FLASH
204 /* UPM Table Configuration Code */
205 static uint UPMATable[] = {
206 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
207 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
211 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
212 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
213 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
217 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
222 };
223 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
224
225 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
226 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
227
228 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
229 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
230 */
231 immap->im_lbc.mamr = 0x08404440;
232
233 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
234
235 puts("UPMA: Configured for compact flash\n");
236 #endif
237
238 return 0;
239 }
240
241 /*
242 * Miscellaneous late-boot configurations
243 *
244 * Make sure the EEPROM has the HRCW correctly programmed.
245 * Make sure the RTC is correctly programmed.
246 *
247 * The MPC8349E-mITX can be configured to load the HRCW from
248 * EEPROM instead of flash. This is controlled via jumpers
249 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
250 * jumpered), but if they're set to 001 or 010, then the HRCW is
251 * read from the "I2C EEPROM".
252 *
253 * This function makes sure that the I2C EEPROM is programmed
254 * correctly.
255 *
256 * If a VSC7385 microcode image is present, then upload it.
257 */
misc_init_r(void)258 int misc_init_r(void)
259 {
260 int rc = 0;
261
262 #if defined(CONFIG_SYS_I2C)
263 unsigned int orig_bus = i2c_get_bus_num();
264 u8 i2c_data;
265
266 #ifdef CONFIG_SYS_I2C_RTC_ADDR
267 u8 ds1339_data[17];
268 #endif
269
270 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
271 static u8 eeprom_data[] = /* HRCW data */
272 {
273 0xAA, 0x55, 0xAA, /* Preamble */
274 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
275 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
276 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
277 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
278 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
279 CONFIG_SYS_HRCW_LOW & 0xFF,
280 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
281 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
282 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
283 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
284 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
285 CONFIG_SYS_HRCW_HIGH & 0xFF
286 };
287
288 u8 data[sizeof(eeprom_data)];
289 #endif
290
291 printf("Board revision: ");
292 i2c_set_bus_num(1);
293 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
294 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
295 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
296 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
297 else {
298 printf("Unknown\n");
299 rc = 1;
300 }
301
302 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
303 i2c_set_bus_num(0);
304
305 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
306 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
307 if (i2c_write
308 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
309 sizeof(eeprom_data)) != 0) {
310 puts("Failure writing the HRCW to EEPROM via I2C.\n");
311 rc = 1;
312 }
313 }
314 } else {
315 puts("Failure reading the HRCW from EEPROM via I2C.\n");
316 rc = 1;
317 }
318 #endif
319
320 #ifdef CONFIG_SYS_I2C_RTC_ADDR
321 i2c_set_bus_num(1);
322
323 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
324 == 0) {
325
326 /* Work-around for MPC8349E-mITX bug #13601.
327 If the RTC does not contain valid register values, the DS1339
328 Linux driver will not work.
329 */
330
331 /* Make sure status register bits 6-2 are zero */
332 ds1339_data[0x0f] &= ~0x7c;
333
334 /* Check for a valid day register value */
335 ds1339_data[0x03] &= ~0xf8;
336 if (ds1339_data[0x03] == 0) {
337 ds1339_data[0x03] = 1;
338 }
339
340 /* Check for a valid date register value */
341 ds1339_data[0x04] &= ~0xc0;
342 if ((ds1339_data[0x04] == 0) ||
343 ((ds1339_data[0x04] & 0x0f) > 9) ||
344 (ds1339_data[0x04] >= 0x32)) {
345 ds1339_data[0x04] = 1;
346 }
347
348 /* Check for a valid month register value */
349 ds1339_data[0x05] &= ~0x60;
350
351 if ((ds1339_data[0x05] == 0) ||
352 ((ds1339_data[0x05] & 0x0f) > 9) ||
353 ((ds1339_data[0x05] >= 0x13)
354 && (ds1339_data[0x05] <= 0x19))) {
355 ds1339_data[0x05] = 1;
356 }
357
358 /* Enable Oscillator and rate select */
359 ds1339_data[0x0e] = 0x1c;
360
361 /* Work-around for MPC8349E-mITX bug #13330.
362 Ensure that the RTC control register contains the value 0x1c.
363 This affects SATA performance.
364 */
365
366 if (i2c_write
367 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
368 sizeof(ds1339_data))) {
369 puts("Failure writing to the RTC via I2C.\n");
370 rc = 1;
371 }
372 } else {
373 puts("Failure reading from the RTC via I2C.\n");
374 rc = 1;
375 }
376 #endif
377
378 i2c_set_bus_num(orig_bus);
379 #endif
380
381 #ifdef CONFIG_VSC7385_IMAGE
382 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
383 CONFIG_VSC7385_IMAGE_SIZE)) {
384 puts("Failure uploading VSC7385 microcode.\n");
385 rc = 1;
386 }
387 #endif
388
389 return rc;
390 }
391
392 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)393 int ft_board_setup(void *blob, struct bd_info *bd)
394 {
395 ft_cpu_setup(blob, bd);
396 #ifdef CONFIG_PCI
397 ft_pci_setup(blob, bd);
398 #endif
399
400 return 0;
401 }
402 #endif
403