1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 */
7
8 #include <common.h>
9 #include <flash.h>
10 #include <init.h>
11 #include <log.h>
12 #include <pci.h>
13 #include <asm/processor.h>
14 #include <asm/mmu.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
18 #include <asm/fsl_serdes.h>
19 #include <spd_sdram.h>
20 #include <i2c.h>
21 #include <ioports.h>
22 #include <linux/delay.h>
23 #include <linux/libfdt.h>
24 #include <fdt_support.h>
25
26 #include "bcsr.h"
27
28 const qe_iop_conf_t qe_iop_conf_tab[] = {
29 /* GETH1 */
30 {4, 10, 1, 0, 2}, /* TxD0 */
31 {4, 9, 1, 0, 2}, /* TxD1 */
32 {4, 8, 1, 0, 2}, /* TxD2 */
33 {4, 7, 1, 0, 2}, /* TxD3 */
34 {4, 23, 1, 0, 2}, /* TxD4 */
35 {4, 22, 1, 0, 2}, /* TxD5 */
36 {4, 21, 1, 0, 2}, /* TxD6 */
37 {4, 20, 1, 0, 2}, /* TxD7 */
38 {4, 15, 2, 0, 2}, /* RxD0 */
39 {4, 14, 2, 0, 2}, /* RxD1 */
40 {4, 13, 2, 0, 2}, /* RxD2 */
41 {4, 12, 2, 0, 2}, /* RxD3 */
42 {4, 29, 2, 0, 2}, /* RxD4 */
43 {4, 28, 2, 0, 2}, /* RxD5 */
44 {4, 27, 2, 0, 2}, /* RxD6 */
45 {4, 26, 2, 0, 2}, /* RxD7 */
46 {4, 11, 1, 0, 2}, /* TX_EN */
47 {4, 24, 1, 0, 2}, /* TX_ER */
48 {4, 16, 2, 0, 2}, /* RX_DV */
49 {4, 30, 2, 0, 2}, /* RX_ER */
50 {4, 17, 2, 0, 2}, /* RX_CLK */
51 {4, 19, 1, 0, 2}, /* GTX_CLK */
52 {1, 31, 2, 0, 3}, /* GTX125 */
53
54 /* GETH2 */
55 {5, 10, 1, 0, 2}, /* TxD0 */
56 {5, 9, 1, 0, 2}, /* TxD1 */
57 {5, 8, 1, 0, 2}, /* TxD2 */
58 {5, 7, 1, 0, 2}, /* TxD3 */
59 {5, 23, 1, 0, 2}, /* TxD4 */
60 {5, 22, 1, 0, 2}, /* TxD5 */
61 {5, 21, 1, 0, 2}, /* TxD6 */
62 {5, 20, 1, 0, 2}, /* TxD7 */
63 {5, 15, 2, 0, 2}, /* RxD0 */
64 {5, 14, 2, 0, 2}, /* RxD1 */
65 {5, 13, 2, 0, 2}, /* RxD2 */
66 {5, 12, 2, 0, 2}, /* RxD3 */
67 {5, 29, 2, 0, 2}, /* RxD4 */
68 {5, 28, 2, 0, 2}, /* RxD5 */
69 {5, 27, 2, 0, 3}, /* RxD6 */
70 {5, 26, 2, 0, 2}, /* RxD7 */
71 {5, 11, 1, 0, 2}, /* TX_EN */
72 {5, 24, 1, 0, 2}, /* TX_ER */
73 {5, 16, 2, 0, 2}, /* RX_DV */
74 {5, 30, 2, 0, 2}, /* RX_ER */
75 {5, 17, 2, 0, 2}, /* RX_CLK */
76 {5, 19, 1, 0, 2}, /* GTX_CLK */
77 {1, 31, 2, 0, 3}, /* GTX125 */
78 {4, 6, 3, 0, 2}, /* MDIO */
79 {4, 5, 1, 0, 2}, /* MDC */
80
81 /* UART1 */
82 {2, 0, 1, 0, 2}, /* UART_SOUT1 */
83 {2, 1, 1, 0, 2}, /* UART_RTS1 */
84 {2, 2, 2, 0, 2}, /* UART_CTS1 */
85 {2, 3, 2, 0, 2}, /* UART_SIN1 */
86
87 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
88 };
89
90 void local_bus_init(void);
91
board_early_init_f(void)92 int board_early_init_f (void)
93 {
94 /*
95 * Initialize local bus.
96 */
97 local_bus_init ();
98
99 enable_8568mds_duart();
100 enable_8568mds_flash_write();
101 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
102 reset_8568mds_uccs();
103 #endif
104 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
105 enable_8568mds_qe_mdio();
106 #endif
107
108 #ifdef CONFIG_SYS_I2C2_OFFSET
109 /* Enable I2C2_SCL and I2C2_SDA */
110 volatile struct par_io *port_c;
111 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
112 port_c->cpdir2 |= 0x0f000000;
113 port_c->cppar2 &= ~0x0f000000;
114 port_c->cppar2 |= 0x0a000000;
115 #endif
116
117 return 0;
118 }
119
checkboard(void)120 int checkboard (void)
121 {
122 printf ("Board: 8568 MDS\n");
123
124 return 0;
125 }
126
127 /*
128 * Initialize Local Bus
129 */
130 void
local_bus_init(void)131 local_bus_init(void)
132 {
133 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
134 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
135
136 uint clkdiv;
137 sys_info_t sysinfo;
138
139 get_sys_info(&sysinfo);
140 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
141
142 gur->lbiuiplldcr1 = 0x00078080;
143 if (clkdiv == 16) {
144 gur->lbiuiplldcr0 = 0x7c0f1bf0;
145 } else if (clkdiv == 8) {
146 gur->lbiuiplldcr0 = 0x6c0f1bf0;
147 } else if (clkdiv == 4) {
148 gur->lbiuiplldcr0 = 0x5c0f1bf0;
149 }
150
151 lbc->lcrr |= 0x00030000;
152
153 asm("sync;isync;msync");
154 }
155
156 /*
157 * Initialize SDRAM memory on the Local Bus.
158 */
lbc_sdram_init(void)159 void lbc_sdram_init(void)
160 {
161 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
162
163 uint idx;
164 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
165 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
166 uint lsdmr_common;
167
168 puts("LBC SDRAM: ");
169 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
170 "\n ");
171
172 /*
173 * Setup SDRAM Base and Option Registers
174 */
175 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
176 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
177 asm("msync");
178
179 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
180 asm("msync");
181
182 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
183 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
184 asm("msync");
185
186 /*
187 * MPC8568 uses "new" 15-16 style addressing.
188 */
189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
190 lsdmr_common |= LSDMR_BSMA1516;
191
192 /*
193 * Issue PRECHARGE ALL command.
194 */
195 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
196 asm("sync;msync");
197 *sdram_addr = 0xff;
198 ppcDcbf((unsigned long) sdram_addr);
199 udelay(100);
200
201 /*
202 * Issue 8 AUTO REFRESH commands.
203 */
204 for (idx = 0; idx < 8; idx++) {
205 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
206 asm("sync;msync");
207 *sdram_addr = 0xff;
208 ppcDcbf((unsigned long) sdram_addr);
209 udelay(100);
210 }
211
212 /*
213 * Issue 8 MODE-set command.
214 */
215 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
216 asm("sync;msync");
217 *sdram_addr = 0xff;
218 ppcDcbf((unsigned long) sdram_addr);
219 udelay(100);
220
221 /*
222 * Issue NORMAL OP command.
223 */
224 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
225 asm("sync;msync");
226 *sdram_addr = 0xff;
227 ppcDcbf((unsigned long) sdram_addr);
228 udelay(200); /* Overkill. Must wait > 200 bus cycles */
229
230 #endif /* enable SDRAM init */
231 }
232
233 #if defined(CONFIG_PCI)
234 #ifndef CONFIG_PCI_PNP
235 static struct pci_config_table pci_mpc8568mds_config_table[] = {
236 {
237 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
238 pci_cfgfunc_config_device,
239 {PCI_ENET0_IOADDR,
240 PCI_ENET0_MEMADDR,
241 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
242 },
243 {}
244 };
245 #endif
246
247 static struct pci_controller pci1_hose;
248 #endif /* CONFIG_PCI */
249
250 /*
251 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
252 */
253 void
pib_init(void)254 pib_init(void)
255 {
256 u8 val8, orig_i2c_bus;
257 /*
258 * Assign PIB PMC2/3 to PCI bus
259 */
260
261 /*switch temporarily to I2C bus #2 */
262 orig_i2c_bus = i2c_get_bus_num();
263 i2c_set_bus_num(1);
264
265 val8 = 0x00;
266 i2c_write(0x23, 0x6, 1, &val8, 1);
267 i2c_write(0x23, 0x7, 1, &val8, 1);
268 val8 = 0xff;
269 i2c_write(0x23, 0x2, 1, &val8, 1);
270 i2c_write(0x23, 0x3, 1, &val8, 1);
271
272 val8 = 0x00;
273 i2c_write(0x26, 0x6, 1, &val8, 1);
274 val8 = 0x34;
275 i2c_write(0x26, 0x7, 1, &val8, 1);
276 val8 = 0xf9;
277 i2c_write(0x26, 0x2, 1, &val8, 1);
278 val8 = 0xff;
279 i2c_write(0x26, 0x3, 1, &val8, 1);
280
281 val8 = 0x00;
282 i2c_write(0x27, 0x6, 1, &val8, 1);
283 i2c_write(0x27, 0x7, 1, &val8, 1);
284 val8 = 0xff;
285 i2c_write(0x27, 0x2, 1, &val8, 1);
286 val8 = 0xef;
287 i2c_write(0x27, 0x3, 1, &val8, 1);
288
289 asm("eieio");
290 i2c_set_bus_num(orig_i2c_bus);
291 }
292
293 #ifdef CONFIG_PCI
pci_init_board(void)294 void pci_init_board(void)
295 {
296 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
297 int first_free_busno = 0;
298 #ifdef CONFIG_PCI1
299 struct fsl_pci_info pci_info;
300 u32 devdisr, pordevsr, io_sel;
301 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
302
303 devdisr = in_be32(&gur->devdisr);
304 pordevsr = in_be32(&gur->pordevsr);
305 porpllsr = in_be32(&gur->porpllsr);
306 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
307
308 debug(" %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel);
309
310 pci_speed = 66666000;
311 pci_32 = 1;
312 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
313 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
314
315 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
316 SET_STD_PCI_INFO(pci_info, 1);
317 set_next_law(pci_info.mem_phys,
318 law_size_bits(pci_info.mem_size), pci_info.law);
319 set_next_law(pci_info.io_phys,
320 law_size_bits(pci_info.io_size), pci_info.law);
321
322 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
323 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
324 (pci_32) ? 32 : 64,
325 (pci_speed == 33333000) ? "33" :
326 (pci_speed == 66666000) ? "66" : "unknown",
327 pci_clk_sel ? "sync" : "async",
328 pci_agent ? "agent" : "host",
329 pci_arb ? "arbiter" : "external-arbiter",
330 pci_info.regs);
331
332 #ifndef CONFIG_PCI_PNP
333 pci1_hose.config_table = pci_mpc8568mds_config_table;
334 #endif
335 first_free_busno = fsl_pci_init_port(&pci_info,
336 &pci1_hose, first_free_busno);
337 } else {
338 printf("PCI: disabled\n");
339 }
340
341 puts("\n");
342 #else
343 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
344 #endif
345
346 fsl_pcie_init_board(first_free_busno);
347 }
348 #endif /* CONFIG_PCI */
349
350 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)351 int ft_board_setup(void *blob, struct bd_info *bd)
352 {
353 ft_cpu_setup(blob, bd);
354
355 FT_FSL_PCI_SETUP;
356
357 return 0;
358 }
359 #endif
360