1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <init.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/global_data.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/io.h>
18 #include <common.h>
19 #include <linux/sizes.h>
20 #include <mmc.h>
21 #include <power/pmic.h>
22 #include <power/pfuze100_pmic.h>
23 #include "../common/pfuze.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
28 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
29 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
30
dram_init(void)31 int dram_init(void)
32 {
33 gd->ram_size = imx_ddr_size();
34
35 return 0;
36 }
37
38 static iomux_v3_cfg_t const uart1_pads[] = {
39 MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
41 };
42
43 static iomux_v3_cfg_t const wdog_pads[] = {
44 MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
45 };
46
setup_iomux_uart(void)47 static void setup_iomux_uart(void)
48 {
49 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
50 }
51
52 #ifdef CONFIG_DM_PMIC_PFUZE100
power_init_board(void)53 int power_init_board(void)
54 {
55 struct udevice *dev;
56 int ret;
57 u32 dev_id, rev_id, i;
58 u32 switch_num = 6;
59 u32 offset = PFUZE100_SW1CMODE;
60
61 ret = pmic_get("pfuze100@08", &dev);
62 if (ret == -ENODEV)
63 return 0;
64
65 if (ret != 0)
66 return ret;
67
68 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
69 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
70 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
71
72
73 /* Init mode to APS_PFM */
74 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
75
76 for (i = 0; i < switch_num - 1; i++)
77 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
78
79 /* set SW1AB staby volatage 0.975V */
80 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
81
82 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
83 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
84
85 /* set SW1C staby volatage 0.975V */
86 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
87
88 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
89 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
90
91 return 0;
92 }
93 #endif
94
board_early_init_f(void)95 int board_early_init_f(void)
96 {
97 setup_iomux_uart();
98
99 return 0;
100 }
101
board_init(void)102 int board_init(void)
103 {
104 /* Address of boot parameters */
105 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
106
107 return 0;
108 }
109
board_late_init(void)110 int board_late_init(void)
111 {
112 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
113
114 return 0;
115 }
116
checkboard(void)117 int checkboard(void)
118 {
119 puts("Board: MX6SLL EVK\n");
120
121 return 0;
122 }
123
board_mmc_get_env_dev(int devno)124 int board_mmc_get_env_dev(int devno)
125 {
126 return devno;
127 }
128
mmc_map_to_kernel_blk(int devno)129 int mmc_map_to_kernel_blk(int devno)
130 {
131 return devno;
132 }
133