1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <clock_legacy.h>
7 #include <console.h>
8 #include <env_internal.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <ns16550.h>
12 #include <nand.h>
13 #include <i2c.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <spi_flash.h>
17 #include <asm/global_data.h>
18 #include "../common/sleep.h"
19 #include "../common/spl.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
get_effective_memsize(void)23 phys_size_t get_effective_memsize(void)
24 {
25 return CONFIG_SYS_L3_SIZE;
26 }
27
get_board_sys_clk(void)28 unsigned long get_board_sys_clk(void)
29 {
30 return CONFIG_SYS_CLK_FREQ;
31 }
32
get_board_ddr_clk(void)33 unsigned long get_board_ddr_clk(void)
34 {
35 return CONFIG_DDR_CLK_FREQ;
36 }
37
38 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
board_init_f(ulong bootflag)39 void board_init_f(ulong bootflag)
40 {
41 u32 plat_ratio, sys_clk, uart_clk;
42 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
43 u32 porsr1, pinctl;
44 u32 svr = get_svr();
45 #endif
46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
47
48 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
49 if (IS_SVR_REV(svr, 1, 0)) {
50 /*
51 * There is T1040 SoC issue where NOR, FPGA are inaccessible
52 * during NAND boot because IFC signals > IFC_AD7 are not
53 * enabled. This workaround changes RCW source to make all
54 * signals enabled.
55 */
56 porsr1 = in_be32(&gur->porsr1);
57 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
58 | 0x24800000);
59 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
60 pinctl);
61 }
62 #endif
63
64 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
65 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
66
67 /* Update GD pointer */
68 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
69
70 #ifdef CONFIG_DEEP_SLEEP
71 /* disable the console if boot from deep sleep */
72 if (is_warm_boot())
73 fsl_dp_disable_console();
74 #endif
75 /* compiler optimization barrier needed for GCC >= 3.4 */
76 __asm__ __volatile__("" : : : "memory");
77
78 console_init_f();
79
80 /* initialize selected port with appropriate baud rate */
81 sys_clk = get_board_sys_clk();
82 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
83 uart_clk = sys_clk * plat_ratio / 2;
84
85 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
86 uart_clk / 16 / CONFIG_BAUDRATE);
87
88 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
89 }
90
board_init_r(gd_t * gd,ulong dest_addr)91 void board_init_r(gd_t *gd, ulong dest_addr)
92 {
93 struct bd_info *bd;
94
95 bd = (struct bd_info *)(gd + sizeof(gd_t));
96 memset(bd, 0, sizeof(struct bd_info));
97 gd->bd = bd;
98
99 arch_cpu_init();
100 get_clocks();
101 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
102 CONFIG_SPL_RELOC_MALLOC_SIZE);
103 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
104
105 #ifdef CONFIG_SPL_MMC_BOOT
106 mmc_initialize(bd);
107 #endif
108
109 /* relocate environment function pointers etc. */
110 #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
111 defined(CONFIG_ENV_IS_IN_SPI_FLASH)
112 #ifdef CONFIG_SPL_NAND_BOOT
113 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
114 (uchar *)SPL_ENV_ADDR);
115 #endif
116 #ifdef CONFIG_SPL_MMC_BOOT
117 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
118 (uchar *)SPL_ENV_ADDR);
119 #endif
120 #ifdef CONFIG_SPL_SPI_BOOT
121 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
122 (uchar *)SPL_ENV_ADDR);
123 #endif
124 gd->env_addr = (ulong)(SPL_ENV_ADDR);
125 gd->env_valid = ENV_VALID;
126 #endif
127
128 i2c_init_all();
129
130 puts("\n\n");
131
132 dram_init();
133
134 #ifdef CONFIG_SPL_MMC_BOOT
135 mmc_boot();
136 #elif defined(CONFIG_SPL_SPI_BOOT)
137 fsl_spi_boot();
138 #elif defined(CONFIG_SPL_NAND_BOOT)
139 nand_boot();
140 #endif
141 }
142