1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 *
5 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <fdt_support.h>
11 #include <net.h>
12 #include <netdev.h>
13 #include <asm/mmu.h>
14 #include <asm/processor.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
20 #include <malloc.h>
21 #include <fm_eth.h>
22 #include <fsl_mdio.h>
23 #include <miiphy.h>
24 #include <phy.h>
25 #include <fsl_dtsec.h>
26 #include <asm/fsl_serdes.h>
27
board_eth_init(struct bd_info * bis)28 int board_eth_init(struct bd_info *bis)
29 {
30 #if defined(CONFIG_FMAN_ENET)
31 int i, interface;
32 struct memac_mdio_info dtsec_mdio_info;
33 struct memac_mdio_info tgec_mdio_info;
34 struct mii_dev *dev;
35 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 u32 srds_s1;
37
38 srds_s1 = in_be32(&gur->rcwsr[4]) &
39 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
40 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
41
42 dtsec_mdio_info.regs =
43 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
44
45 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
46
47 /* Register the 1G MDIO bus */
48 fm_memac_mdio_init(bis, &dtsec_mdio_info);
49
50 tgec_mdio_info.regs =
51 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
52 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
53
54 /* Register the 10G MDIO bus */
55 fm_memac_mdio_init(bis, &tgec_mdio_info);
56
57 /* Set the two on-board RGMII PHY address */
58 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
59 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
60
61 switch (srds_s1) {
62 case 0x66:
63 case 0x6b:
64 fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
65 fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
66 fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
67 fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
68 break;
69 default:
70 printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
71 srds_s1);
72 break;
73 }
74
75 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
76 interface = fm_info_get_enet_if(i);
77 switch (interface) {
78 case PHY_INTERFACE_MODE_RGMII:
79 case PHY_INTERFACE_MODE_RGMII_TXID:
80 case PHY_INTERFACE_MODE_RGMII_RXID:
81 case PHY_INTERFACE_MODE_RGMII_ID:
82 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
83 fm_info_set_mdio(i, dev);
84 break;
85 default:
86 break;
87 }
88 }
89
90 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
91 switch (fm_info_get_enet_if(i)) {
92 case PHY_INTERFACE_MODE_XGMII:
93 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
94 fm_info_set_mdio(i, dev);
95 break;
96 default:
97 break;
98 }
99 }
100
101 cpu_eth_init(bis);
102 #endif /* CONFIG_FMAN_ENET */
103
104 return pci_eth_init(bis);
105 }
106
fdt_fixup_board_enet(void * fdt)107 void fdt_fixup_board_enet(void *fdt)
108 {
109 return;
110 }
111