1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Timesys Corporation
4 * Copyright 2015 General Electric Company
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 */
7
8 #include <image.h>
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <env.h>
15 #include <asm/global_data.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/libfdt.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/video.h>
23 #include <mmc.h>
24 #include <fsl_esdhc_imx.h>
25 #include <miiphy.h>
26 #include <net.h>
27 #include <netdev.h>
28 #include <asm/arch/mxc_hdmi.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/io.h>
31 #include <asm/arch/sys_proto.h>
32 #include <power/regulator.h>
33 #include <power/da9063_pmic.h>
34 #include <input.h>
35 #include <pwm.h>
36 #include <version.h>
37 #include <stdlib.h>
38 #include <dm/root.h>
39 #include "../common/ge_rtc.h"
40 #include "../common/vpd_reader.h"
41 #include "../../../drivers/net/e1000.h"
42 #include <pci.h>
43 #include <panel.h>
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47 #define VPD_PRODUCT_B850 1
48 #define VPD_PRODUCT_B650 2
49 #define VPD_PRODUCT_B450 3
50
51 #define AR8033_DBG_REG_ADDR 0x1d
52 #define AR8033_DBG_REG_DATA 0x1e
53 #define AR8033_SERDES_REG 0x5
54
55 static int productid; /* Default to generic. */
56 static struct vpd_cache vpd;
57
58 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
60 PAD_CTL_HYS)
61
dram_init(void)62 int dram_init(void)
63 {
64 gd->ram_size = imx_ddr_size();
65
66 return 0;
67 }
68
board_phy_config(struct phy_device * phydev)69 int board_phy_config(struct phy_device *phydev)
70 {
71 /*
72 * Set reserved bits to avoid board specific voltage peak issue. The
73 * value is a magic number provided directly by Qualcomm. Note, that
74 * PHY driver will take control of BIT(8) in this register to control
75 * TX clock delay, so we do not initialize that bit here.
76 */
77 phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
78 phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
79
80 if (phydev->drv->config)
81 phydev->drv->config(phydev);
82
83 return 0;
84 }
85
86 #if defined(CONFIG_VIDEO_IPUV3)
do_enable_backlight(struct display_info_t const * dev)87 static void do_enable_backlight(struct display_info_t const *dev)
88 {
89 struct udevice *panel;
90 int ret;
91
92 ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
93 if (ret) {
94 printf("Could not find panel: %d\n", ret);
95 return;
96 }
97
98 panel_set_backlight(panel, 100);
99 panel_enable_backlight(panel);
100 }
101
do_enable_hdmi(struct display_info_t const * dev)102 static void do_enable_hdmi(struct display_info_t const *dev)
103 {
104 imx_enable_hdmi_phy();
105 }
106
is_b850v3(void)107 static int is_b850v3(void)
108 {
109 return productid == VPD_PRODUCT_B850;
110 }
111
detect_lcd(struct display_info_t const * dev)112 static int detect_lcd(struct display_info_t const *dev)
113 {
114 return !is_b850v3();
115 }
116
117 struct display_info_t const displays[] = {{
118 .bus = -1,
119 .addr = -1,
120 .pixfmt = IPU_PIX_FMT_RGB24,
121 .detect = detect_lcd,
122 .enable = do_enable_backlight,
123 .mode = {
124 .name = "G121X1-L03",
125 .refresh = 60,
126 .xres = 1024,
127 .yres = 768,
128 .pixclock = 15385,
129 .left_margin = 20,
130 .right_margin = 300,
131 .upper_margin = 30,
132 .lower_margin = 8,
133 .hsync_len = 1,
134 .vsync_len = 1,
135 .sync = FB_SYNC_EXT,
136 .vmode = FB_VMODE_NONINTERLACED
137 } }, {
138 .bus = -1,
139 .addr = 3,
140 .pixfmt = IPU_PIX_FMT_RGB24,
141 .detect = detect_hdmi,
142 .enable = do_enable_hdmi,
143 .mode = {
144 .name = "HDMI",
145 .refresh = 60,
146 .xres = 1024,
147 .yres = 768,
148 .pixclock = 15385,
149 .left_margin = 220,
150 .right_margin = 40,
151 .upper_margin = 21,
152 .lower_margin = 7,
153 .hsync_len = 60,
154 .vsync_len = 10,
155 .sync = FB_SYNC_EXT,
156 .vmode = FB_VMODE_NONINTERLACED
157 } } };
158 size_t display_count = ARRAY_SIZE(displays);
159
enable_videopll(void)160 static void enable_videopll(void)
161 {
162 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
163 s32 timeout = 100000;
164
165 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
166
167 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
168 * |
169 * PLL5
170 * |
171 * CS2CDR[LDB_DI0_CLK_SEL]
172 * |
173 * +----> LDB_DI0_SERIAL_CLK_ROOT
174 * |
175 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
176 */
177
178 clrsetbits_le32(&ccm->analog_pll_video,
179 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
180 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
181 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
182 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
183
184 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
185 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
186
187 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
188
189 while (timeout--)
190 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
191 break;
192
193 if (timeout < 0)
194 printf("Warning: video pll lock timeout!\n");
195
196 clrsetbits_le32(&ccm->analog_pll_video,
197 BM_ANADIG_PLL_VIDEO_BYPASS,
198 BM_ANADIG_PLL_VIDEO_ENABLE);
199 }
200
setup_display_b850v3(void)201 static void setup_display_b850v3(void)
202 {
203 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
204 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
205
206 enable_videopll();
207
208 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
209 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
210
211 imx_setup_hdmi();
212
213 /* Set LDB_DI0 as clock source for IPU_DI0 */
214 clrsetbits_le32(&mxc_ccm->chsccdr,
215 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
216 (CHSCCDR_CLK_SEL_LDB_DI0 <<
217 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
218
219 /* Turn on IPU LDB DI0 clocks */
220 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
221
222 enable_ipu_clock();
223
224 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
225 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
226 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
227 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
228 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
229 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
230 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
231 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
232 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
233 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
234 &iomux->gpr[2]);
235
236 clrbits_le32(&iomux->gpr[3],
237 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
238 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
239 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
240 }
241
setup_display_bx50v3(void)242 static void setup_display_bx50v3(void)
243 {
244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
245 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
246
247 enable_videopll();
248
249 /* When a reset/reboot is performed the display power needs to be turned
250 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
251 * an additional 200ms here. Unfortunately we use external PMIC for
252 * doing the reset, so can not differentiate between POR vs soft reset
253 */
254 mdelay(200);
255
256 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
257 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
258
259 /* Set LDB_DI0 as clock source for IPU_DI0 */
260 clrsetbits_le32(&mxc_ccm->chsccdr,
261 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
262 (CHSCCDR_CLK_SEL_LDB_DI0 <<
263 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
264
265 /* Turn on IPU LDB DI0 clocks */
266 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
267
268 enable_ipu_clock();
269
270 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
271 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
272 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
273 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
274 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
275 &iomux->gpr[2]);
276
277 clrsetbits_le32(&iomux->gpr[3],
278 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
279 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
280 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
281 }
282 #endif /* CONFIG_VIDEO_IPUV3 */
283
284 /*
285 * Do not overwrite the console
286 * Use always serial for U-Boot console
287 */
overwrite_console(void)288 int overwrite_console(void)
289 {
290 return 1;
291 }
292
293 #define VPD_TYPE_INVALID 0x00
294 #define VPD_BLOCK_NETWORK 0x20
295 #define VPD_BLOCK_HWID 0x44
296 #define VPD_HAS_MAC1 0x1
297 #define VPD_HAS_MAC2 0x2
298 #define VPD_MAC_ADDRESS_LENGTH 6
299
300 struct vpd_cache {
301 bool is_read;
302 u8 product_id;
303 u8 has;
304 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
305 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
306 };
307
308 /*
309 * Extracts MAC and product information from the VPD.
310 */
vpd_callback(struct vpd_cache * vpd,u8 id,u8 version,u8 type,size_t size,u8 const * data)311 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
312 size_t size, u8 const *data)
313 {
314 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
315 size >= 1) {
316 vpd->product_id = data[0];
317 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
318 type != VPD_TYPE_INVALID) {
319 if (size >= 6) {
320 vpd->has |= VPD_HAS_MAC1;
321 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
322 }
323 if (size >= 12) {
324 vpd->has |= VPD_HAS_MAC2;
325 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
326 }
327 }
328
329 return 0;
330 }
331
process_vpd(struct vpd_cache * vpd)332 static void process_vpd(struct vpd_cache *vpd)
333 {
334 int fec_index = 0;
335 int i210_index = -1;
336
337 if (!vpd->is_read) {
338 printf("VPD wasn't read");
339 return;
340 }
341
342 if (vpd->has & VPD_HAS_MAC1)
343 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
344
345 env_set("ethact", "eth0");
346
347 switch (vpd->product_id) {
348 case VPD_PRODUCT_B450:
349 i210_index = 1;
350 break;
351 case VPD_PRODUCT_B650:
352 i210_index = 1;
353 break;
354 case VPD_PRODUCT_B850:
355 i210_index = 2;
356 break;
357 }
358
359 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
360 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
361 }
362
363 static iomux_v3_cfg_t const misc_pads[] = {
364 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
365 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
366 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
367 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
368 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
369 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
370 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
371 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
372 };
373 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
374 #define PWGIN_IN IMX_GPIO_NR(4, 14)
375 #define WIFI_EN IMX_GPIO_NR(6, 14)
376
board_early_init_f(void)377 int board_early_init_f(void)
378 {
379 imx_iomux_v3_setup_multiple_pads(misc_pads,
380 ARRAY_SIZE(misc_pads));
381
382 #if defined(CONFIG_VIDEO_IPUV3)
383 /* Set LDB clock to Video PLL */
384 select_ldb_di_clock_source(MXC_PLL5_CLK);
385 #endif
386 return 0;
387 }
388
board_init(void)389 int board_init(void)
390 {
391 if (!read_i2c_vpd(&vpd, vpd_callback)) {
392 int ret, rescan;
393
394 vpd.is_read = true;
395 productid = vpd.product_id;
396
397 ret = fdtdec_resetup(&rescan);
398 if (!ret && rescan) {
399 dm_uninit();
400 dm_init_and_scan(false);
401 }
402 }
403
404 gpio_request(SUS_S3_OUT, "sus_s3_out");
405 gpio_direction_output(SUS_S3_OUT, 1);
406
407 gpio_request(PWGIN_IN, "pwgin_in");
408 gpio_direction_input(PWGIN_IN);
409
410 gpio_request(WIFI_EN, "wifi_en");
411 gpio_direction_output(WIFI_EN, 1);
412
413 #if defined(CONFIG_VIDEO_IPUV3)
414 if (is_b850v3())
415 setup_display_b850v3();
416 else
417 setup_display_bx50v3();
418 #endif
419
420 /* address of boot parameters */
421 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
422
423 return 0;
424 }
425
426 #ifdef CONFIG_CMD_BMODE
427 static const struct boot_mode board_boot_modes[] = {
428 /* 4 bit bus width */
429 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
430 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
431 {NULL, 0},
432 };
433 #endif
434
pmic_init(void)435 void pmic_init(void)
436 {
437 struct udevice *reg;
438 int ret, i;
439 static const char * const bucks[] = {
440 "bcore1",
441 "bcore2",
442 "bpro",
443 "bmem",
444 "bio",
445 "bperi",
446 };
447
448 for (i = 0; i < ARRAY_SIZE(bucks); i++) {
449 ret = regulator_get_by_devname(bucks[i], ®);
450 if (reg < 0) {
451 printf("%s(): Unable to get regulator %s: %d\n",
452 __func__, bucks[i], ret);
453 continue;
454 }
455 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
456 }
457 }
458
detect_boot_cause(void)459 static void detect_boot_cause(void)
460 {
461 const char *cause = "POR";
462
463 if (is_b850v3())
464 if (!gpio_get_value(PWGIN_IN))
465 cause = "PM_WDOG";
466
467 env_set("bootcause", cause);
468 }
469
board_late_init(void)470 int board_late_init(void)
471 {
472 process_vpd(&vpd);
473
474 #ifdef CONFIG_CMD_BMODE
475 add_board_boot_modes(board_boot_modes);
476 #endif
477
478 if (is_b850v3())
479 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
480 else
481 env_set("videoargs", "video=LVDS-1:1024x768@65");
482
483 detect_boot_cause();
484
485 /* board specific pmic init */
486 pmic_init();
487
488 check_time();
489
490 pci_init();
491
492 return 0;
493 }
494
495 /*
496 * Removes the 'eth[0-9]*addr' environment variable with the given index
497 *
498 * @param index [in] the index of the eth_device whose variable is to be removed
499 */
remove_ethaddr_env_var(int index)500 static void remove_ethaddr_env_var(int index)
501 {
502 char env_var_name[9];
503
504 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
505 env_set(env_var_name, NULL);
506 }
507
last_stage_init(void)508 int last_stage_init(void)
509 {
510 int i;
511
512 /*
513 * Remove first three ethaddr which may have been created by
514 * function process_vpd().
515 */
516 for (i = 0; i < 3; ++i)
517 remove_ethaddr_env_var(i);
518
519 return 0;
520 }
521
checkboard(void)522 int checkboard(void)
523 {
524 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
525 return 0;
526 }
527
528 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)529 int ft_board_setup(void *blob, struct bd_info *bd)
530 {
531 char *rtc_status = env_get("rtc_status");
532
533 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
534 strlen(version_string) + 1);
535
536 fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
537 strlen(rtc_status) + 1);
538 return 0;
539 }
540 #endif
541
board_fit_config_name_match(const char * name)542 int board_fit_config_name_match(const char *name)
543 {
544 const char *machine = name;
545
546 if (!vpd.is_read)
547 return strcmp(name, "imx6q-bx50v3");
548
549 if (!strncmp(machine, "Boot ", 5))
550 machine += 5;
551 if (!strncmp(machine, "imx6q-", 6))
552 machine += 6;
553
554 switch (vpd.product_id) {
555 case VPD_PRODUCT_B450:
556 return strcasecmp(machine, "b450v3");
557 case VPD_PRODUCT_B650:
558 return strcasecmp(machine, "b650v3");
559 case VPD_PRODUCT_B850:
560 return strcasecmp(machine, "b850v3");
561 default:
562 return -1;
563 }
564 }
565
embedded_dtb_select(void)566 int embedded_dtb_select(void)
567 {
568 vpd.is_read = false;
569 return fdtdec_setup();
570 }
571