1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
4 *
5 * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
6 */
7
8 #include <common.h>
9 #include <env.h>
10 #include <errno.h>
11 #include <init.h>
12 #include <malloc.h>
13 #include <net.h>
14 #include <serial.h>
15 #include <spl.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <i2c.h>
29 #include <miiphy.h>
30 #include <cpsw.h>
31 #include <fdt_support.h>
32 #include <mtd_node.h>
33 #include <jffs2/load_kernel.h>
34 #include "board.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
39 * and control IGEP0034 green and red LEDs.
40 * U-boot configures these pins as input pullup to detect board revision:
41 * IGEP0034-LITE = 0b00
42 * IGEP0034 (FULL) = 0b01
43 * IGEP0033 = 0b1X
44 */
45 #define GPIO_GREEN_REVISION 27
46 #define GPIO_RED_REVISION 26
47
48 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
49
50 /*
51 * Routine: get_board_revision
52 * Description: Returns the board revision
53 */
get_board_revision(void)54 static int get_board_revision(void)
55 {
56 int revision;
57
58 gpio_request(GPIO_GREEN_REVISION, "green_revision");
59 gpio_direction_input(GPIO_GREEN_REVISION);
60 revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
61 gpio_free(GPIO_GREEN_REVISION);
62
63 gpio_request(GPIO_RED_REVISION, "red_revision");
64 gpio_direction_input(GPIO_RED_REVISION);
65 revision = revision + gpio_get_value(GPIO_RED_REVISION);
66 gpio_free(GPIO_RED_REVISION);
67
68 return revision;
69 }
70
71 #ifdef CONFIG_SPL_BUILD
72 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
73 static const struct ddr_data ddr3_igep0034_data = {
74 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
75 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
76 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
77 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
78 };
79
80 static const struct ddr_data ddr3_igep0034_lite_data = {
81 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
82 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
83 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
84 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
85 };
86
87 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
88 .cmd0csratio = MT41K256M16HA125E_RATIO,
89 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
90
91 .cmd1csratio = MT41K256M16HA125E_RATIO,
92 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
93
94 .cmd2csratio = MT41K256M16HA125E_RATIO,
95 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
96 };
97
98 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
99 .cmd0csratio = K4B2G1646EBIH9_RATIO,
100 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
101
102 .cmd1csratio = K4B2G1646EBIH9_RATIO,
103 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
104
105 .cmd2csratio = K4B2G1646EBIH9_RATIO,
106 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
107 };
108
109 static struct emif_regs ddr3_igep0034_emif_reg_data = {
110 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
111 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
112 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
113 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
114 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
115 .zq_config = MT41K256M16HA125E_ZQ_CFG,
116 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
117 };
118
119 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
120 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
121 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
122 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
123 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
124 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
125 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
126 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
127 };
128
129 const struct ctrl_ioregs ioregs_igep0034 = {
130 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
131 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
132 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
133 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
134 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
135 };
136
137 const struct ctrl_ioregs ioregs_igep0034_lite = {
138 .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
139 .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
140 .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
141 .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
142 .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
143 };
144
145 #define OSC (V_OSCK/1000000)
146 const struct dpll_params dpll_ddr = {
147 400, OSC-1, 1, -1, -1, -1, -1};
148
get_dpll_ddr_params(void)149 const struct dpll_params *get_dpll_ddr_params(void)
150 {
151 return &dpll_ddr;
152 }
153
set_uart_mux_conf(void)154 void set_uart_mux_conf(void)
155 {
156 enable_uart0_pin_mux();
157 }
158
set_mux_conf_regs(void)159 void set_mux_conf_regs(void)
160 {
161 enable_board_pin_mux();
162 }
163
sdram_init(void)164 void sdram_init(void)
165 {
166 if (get_board_revision() == 1)
167 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
168 &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
169 else
170 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
171 &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
172 }
173
174 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)175 int spl_start_uboot(void)
176 {
177 /* break into full u-boot on 'c' */
178 return serial_tstc() && serial_getc() == 'c';
179 }
180 #endif
181 #endif
182
183 /*
184 * Basic board specific setup. Pinmux has been handled already.
185 */
board_init(void)186 int board_init(void)
187 {
188 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
189
190 gpmc_init();
191
192 return 0;
193 }
194
195 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)196 int board_late_init(void)
197 {
198 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
199 switch (get_board_revision()) {
200 case 0:
201 env_set("board_name", "igep0034-lite");
202 break;
203 case 1:
204 env_set("board_name", "igep0034");
205 break;
206 default:
207 env_set("board_name", "igep0033");
208 break;
209 }
210 #endif
211 return 0;
212 }
213 #endif
214
215 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)216 int ft_board_setup(void *blob, struct bd_info *bd)
217 {
218 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
219 static const struct node_info nodes[] = {
220 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
221 };
222
223 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
224 #endif
225 return 0;
226 }
227 #endif
228
229 #if defined(CONFIG_DRIVER_TI_CPSW)
cpsw_control(int enabled)230 static void cpsw_control(int enabled)
231 {
232 /* VTP can be added here */
233
234 return;
235 }
236
237 static struct cpsw_slave_data cpsw_slaves[] = {
238 {
239 .slave_reg_ofs = 0x208,
240 .sliver_reg_ofs = 0xd80,
241 .phy_addr = 0,
242 .phy_if = PHY_INTERFACE_MODE_RMII,
243 },
244 };
245
246 static struct cpsw_platform_data cpsw_data = {
247 .mdio_base = CPSW_MDIO_BASE,
248 .cpsw_base = CPSW_BASE,
249 .mdio_div = 0xff,
250 .channels = 8,
251 .cpdma_reg_ofs = 0x800,
252 .slaves = 1,
253 .slave_data = cpsw_slaves,
254 .ale_reg_ofs = 0xd00,
255 .ale_entries = 1024,
256 .host_port_reg_ofs = 0x108,
257 .hw_stats_reg_ofs = 0x900,
258 .bd_ram_ofs = 0x2000,
259 .mac_control = (1 << 5),
260 .control = cpsw_control,
261 .host_port_num = 0,
262 .version = CPSW_CTRL_VERSION_2,
263 };
264
board_eth_init(struct bd_info * bis)265 int board_eth_init(struct bd_info *bis)
266 {
267 int rv, ret = 0;
268 uint8_t mac_addr[6];
269 uint32_t mac_hi, mac_lo;
270
271 if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
272 /* try reading mac address from efuse */
273 mac_lo = readl(&cdev->macid0l);
274 mac_hi = readl(&cdev->macid0h);
275 mac_addr[0] = mac_hi & 0xFF;
276 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
277 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
278 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
279 mac_addr[4] = mac_lo & 0xFF;
280 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
281 if (is_valid_ethaddr(mac_addr))
282 eth_env_set_enetaddr("ethaddr", mac_addr);
283 }
284
285 writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
286 &cdev->miisel);
287
288 if (get_board_revision() == 1)
289 cpsw_slaves[0].phy_addr = 1;
290
291 rv = cpsw_register(&cpsw_data);
292 if (rv < 0)
293 printf("Error %d registering CPSW switch\n", rv);
294 else
295 ret += rv;
296
297 return ret;
298 }
299 #endif
300