1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Wandboard
4 * Author: Tungyi Lin <tungyilin1127@gmail.com>
5 * Richard Hu <hakahu@gmail.com>
6 */
7
8 #include <image.h>
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <errno.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/video.h>
18 #include <mmc.h>
19 #include <fsl_esdhc_imx.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/io.h>
22 #include <asm/arch/sys_proto.h>
23 #include <serial.h>
24 #include <spl.h>
25 #include <linux/delay.h>
26
27 #include <asm/arch/mx6-ddr.h>
28 /*
29 * Driving strength:
30 * 0x30 == 40 Ohm
31 * 0x28 == 48 Ohm
32 */
33
34 #define IMX6DQ_DRIVE_STRENGTH 0x30
35 #define IMX6SDL_DRIVE_STRENGTH 0x28
36
37 /* configure MX6Q/DUAL mmdc DDR io registers */
38 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
39 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
40 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
41 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
42 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
43 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
44 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
45 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
46 .dram_sdba2 = 0x00000000,
47 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
48 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
49 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
50 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
51 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
52 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
53 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
54 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
55 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
56 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
57 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
58 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
59 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
60 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
61 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
62 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
63 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
64 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
65 };
66
67 /* configure MX6Q/DUAL mmdc GRP io registers */
68 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
69 .grp_ddr_type = 0x000c0000,
70 .grp_ddrmode_ctl = 0x00020000,
71 .grp_ddrpke = 0x00000000,
72 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
73 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
74 .grp_ddrmode = 0x00020000,
75 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
76 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
77 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
78 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
79 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
80 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
81 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
82 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
83 };
84
85 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
86 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
87 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
88 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
89 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
90 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
91 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
92 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
93 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
94 .dram_sdba2 = 0x00000000,
95 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
96 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
97 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
98 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
99 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
100 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
101 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
102 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
103 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
104 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
105 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
106 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
107 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
108 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
109 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
110 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
111 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
112 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
113 };
114
115 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
116 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
117 .grp_ddr_type = 0x000c0000,
118 .grp_ddrmode_ctl = 0x00020000,
119 .grp_ddrpke = 0x00000000,
120 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
121 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
122 .grp_ddrmode = 0x00020000,
123 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
124 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
125 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
126 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
127 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
128 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
129 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
130 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
131 };
132
133 /* H5T04G63AFR-PB */
134 static struct mx6_ddr3_cfg h5t04g63afr = {
135 .mem_speed = 1600,
136 .density = 4,
137 .width = 16,
138 .banks = 8,
139 .rowaddr = 15,
140 .coladdr = 10,
141 .pagesz = 2,
142 .trcd = 1375,
143 .trcmin = 4875,
144 .trasmin = 3500,
145 };
146
147 /* H5TQ2G63DFR-H9 */
148 static struct mx6_ddr3_cfg h5tq2g63dfr = {
149 .mem_speed = 1333,
150 .density = 2,
151 .width = 16,
152 .banks = 8,
153 .rowaddr = 14,
154 .coladdr = 10,
155 .pagesz = 2,
156 .trcd = 1350,
157 .trcmin = 4950,
158 .trasmin = 3600,
159 };
160
161 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
162 .p0_mpwldectrl0 = 0x001f001f,
163 .p0_mpwldectrl1 = 0x001f001f,
164 .p1_mpwldectrl0 = 0x001f001f,
165 .p1_mpwldectrl1 = 0x001f001f,
166 .p0_mpdgctrl0 = 0x4301030d,
167 .p0_mpdgctrl1 = 0x03020277,
168 .p1_mpdgctrl0 = 0x4300030a,
169 .p1_mpdgctrl1 = 0x02780248,
170 .p0_mprddlctl = 0x4536393b,
171 .p1_mprddlctl = 0x36353441,
172 .p0_mpwrdlctl = 0x41414743,
173 .p1_mpwrdlctl = 0x462f453f,
174 };
175
176 /* DDR 64bit 2GB */
177 static struct mx6_ddr_sysinfo mem_q = {
178 .dsize = 2,
179 .cs1_mirror = 0,
180 /* config for full 4GB range so that get_mem_size() works */
181 .cs_density = 32,
182 .ncs = 1,
183 .bi_on = 1,
184 .rtt_nom = 1,
185 .rtt_wr = 0,
186 .ralat = 5,
187 .walat = 0,
188 .mif3_mode = 3,
189 .rst_to_cke = 0x23,
190 .sde_to_rst = 0x10,
191 };
192
193 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
194 .p0_mpwldectrl0 = 0x001f001f,
195 .p0_mpwldectrl1 = 0x001f001f,
196 .p1_mpwldectrl0 = 0x001f001f,
197 .p1_mpwldectrl1 = 0x001f001f,
198 .p0_mpdgctrl0 = 0x420e020e,
199 .p0_mpdgctrl1 = 0x02000200,
200 .p1_mpdgctrl0 = 0x42020202,
201 .p1_mpdgctrl1 = 0x01720172,
202 .p0_mprddlctl = 0x494c4f4c,
203 .p1_mprddlctl = 0x4a4c4c49,
204 .p0_mpwrdlctl = 0x3f3f3133,
205 .p1_mpwrdlctl = 0x39373f2e,
206 };
207
208 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
209 .p0_mpwldectrl0 = 0x0040003c,
210 .p0_mpwldectrl1 = 0x0032003e,
211 .p0_mpdgctrl0 = 0x42350231,
212 .p0_mpdgctrl1 = 0x021a0218,
213 .p0_mprddlctl = 0x4b4b4e49,
214 .p0_mpwrdlctl = 0x3f3f3035,
215 };
216
217 /* DDR 64bit 1GB */
218 static struct mx6_ddr_sysinfo mem_dl = {
219 .dsize = 2,
220 .cs1_mirror = 0,
221 /* config for full 4GB range so that get_mem_size() works */
222 .cs_density = 32,
223 .ncs = 1,
224 .bi_on = 1,
225 .rtt_nom = 1,
226 .rtt_wr = 0,
227 .ralat = 5,
228 .walat = 0,
229 .mif3_mode = 3,
230 .rst_to_cke = 0x23,
231 .sde_to_rst = 0x10,
232 };
233
234 /* DDR 32bit 512MB */
235 static struct mx6_ddr_sysinfo mem_s = {
236 .dsize = 1,
237 .cs1_mirror = 0,
238 /* config for full 4GB range so that get_mem_size() works */
239 .cs_density = 32,
240 .ncs = 1,
241 .bi_on = 1,
242 .rtt_nom = 1,
243 .rtt_wr = 0,
244 .ralat = 5,
245 .walat = 0,
246 .mif3_mode = 3,
247 .rst_to_cke = 0x23,
248 .sde_to_rst = 0x10,
249 };
250
ccgr_init(void)251 static void ccgr_init(void)
252 {
253 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
254
255 writel(0x00C03F3F, &ccm->CCGR0);
256 writel(0x0030FC03, &ccm->CCGR1);
257 writel(0x0FFFC000, &ccm->CCGR2);
258 writel(0x3FF00000, &ccm->CCGR3);
259 writel(0x00FFF300, &ccm->CCGR4);
260 writel(0x0F0000C3, &ccm->CCGR5);
261 writel(0x000003FF, &ccm->CCGR6);
262 }
263
spl_dram_init(void)264 static void spl_dram_init(void)
265 {
266 if (is_cpu_type(MXC_CPU_MX6SOLO)) {
267 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
268 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
269 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
270 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
271 mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
272 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
273 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
274 mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
275 }
276
277 udelay(100);
278 }
279
setup_spi(void)280 static void setup_spi(void)
281 {
282 enable_spi_clk(true, 2);
283 }
284
285 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
286 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
287 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
288
289 static iomux_v3_cfg_t const uart1_pads[] = {
290 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
291 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
292 };
293
setup_iomux_uart(void)294 static void setup_iomux_uart(void)
295 {
296 SETUP_IOMUX_PADS(uart1_pads);
297 }
298
board_init_f(ulong dummy)299 void board_init_f(ulong dummy)
300 {
301 ccgr_init();
302
303 /* setup AIPS and disable watchdog */
304 arch_cpu_init();
305
306 gpr_init();
307
308 /* iomux */
309 setup_iomux_uart();
310
311 /* setup GP timer */
312 timer_init();
313
314 /* UART clocks enabled and gd valid - init serial console */
315 preloader_console_init();
316
317 /* enable ECSPI clocks */
318 setup_spi();
319
320 /* DDR initialization */
321 spl_dram_init();
322 }
323
board_boot_order(u32 * spl_boot_list)324 void board_boot_order(u32 *spl_boot_list)
325 {
326 switch (spl_boot_device()) {
327 case BOOT_DEVICE_MMC2:
328 case BOOT_DEVICE_MMC1:
329 spl_boot_list[0] = BOOT_DEVICE_MMC2;
330 spl_boot_list[1] = BOOT_DEVICE_MMC1;
331 break;
332
333 case BOOT_DEVICE_NOR:
334 spl_boot_list[0] = BOOT_DEVICE_NOR;
335 break;
336 }
337 }
338
339 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)340 int board_fit_config_name_match(const char *name)
341 {
342 return 0;
343 }
344 #endif
345
346 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)347 int spl_start_uboot(void)
348 {
349 char s[16];
350 int ret;
351 /*
352 * We use BOOT_DEVICE_MMC1, but SD card is connected
353 * to MMC2
354 *
355 * Correct "mapping" is delivered in board defined
356 * board_boot_order() function.
357 *
358 * SD card boot is regarded as a "development" one,
359 * hence we _always_ go through the u-boot.
360 *
361 */
362 if (spl_boot_device() == BOOT_DEVICE_MMC1)
363 return 1;
364
365 /* break into full u-boot on 'c' */
366 if (serial_tstc() && serial_getc() == 'c')
367 return 1;
368
369 env_init();
370 ret = env_get_f("boot_os", s, sizeof(s));
371 if ((ret != -1) && (strcmp(s, "no") == 0))
372 return 1;
373
374 /*
375 * Check if SWUpdate recovery needs to be started
376 *
377 * recovery_status = NULL (not set - ret == -1) -> normal operation
378 *
379 * recovery_status = progress or
380 * recovery_status = failed or
381 * recovery_status = <any value> -> start SWUpdate
382 *
383 */
384 ret = env_get_f("recovery_status", s, sizeof(s));
385 if (ret != -1)
386 return 1;
387
388 return 0;
389 }
390 #endif /* CONFIG_SPL_OS_BOOT */
391
392 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
393 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
394 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
395
396 #define NOR_WP IMX_GPIO_NR(1, 1)
397
398 static iomux_v3_cfg_t const eimnor_pads[] = {
399 IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
400 IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
401 IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
402 IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
403 IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
404 IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
405 IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
406 IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
407 IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
408 IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
409 IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
410 IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
411 IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
412 IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
413 IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
414 IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
415 IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
416 IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
417 IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
418 IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
419 IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
420 IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
421 IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
422 IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
423 IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
424 IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
425 IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
426 IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
427 IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
428 IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
429 IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
430 IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
431 IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
432 IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
433 IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
434 IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
435 IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
436 IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
437 IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
438 IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
439 IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
440 IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
441 IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
442 IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
443 IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
444 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
445 };
446
eimnor_cs_setup(void)447 static void eimnor_cs_setup(void)
448 {
449 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
450
451 /* NOR configuration */
452 writel(0x00620181, &weim_regs->cs0gcr1);
453 writel(0x00000001, &weim_regs->cs0gcr2);
454 writel(0x0b020000, &weim_regs->cs0rcr1);
455 writel(0x0000b000, &weim_regs->cs0rcr2);
456 writel(0x0804a240, &weim_regs->cs0wcr1);
457 writel(0x00000000, &weim_regs->cs0wcr2);
458
459 writel(0x00000120, &weim_regs->wcr);
460 writel(0x00000010, &weim_regs->wiar);
461 writel(0x00000000, &weim_regs->ear);
462
463 set_chipselect_size(CS0_128);
464 }
465
setup_eimnor(void)466 static void setup_eimnor(void)
467 {
468 SETUP_IOMUX_PADS(eimnor_pads);
469 gpio_direction_output(NOR_WP, 1);
470
471 enable_eim_clk(1);
472 eimnor_cs_setup();
473 }
474
475 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
476 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
477 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
478
479 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
480
481 static iomux_v3_cfg_t const usdhc2_pads[] = {
482 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
483 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
484 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
485 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
486 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
487 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
488 /* Carrier MicroSD Card Detect */
489 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
490 };
491
492 static iomux_v3_cfg_t const usdhc3_pads[] = {
493 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
494 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
495 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
496 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
497 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
498 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
499 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
500 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
501 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
502 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
503 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
504 };
505
506 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
507 {USDHC3_BASE_ADDR},
508 {USDHC2_BASE_ADDR},
509 };
510
board_mmc_getcd(struct mmc * mmc)511 int board_mmc_getcd(struct mmc *mmc)
512 {
513 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
514 int ret = 0;
515
516 switch (cfg->esdhc_base) {
517 case USDHC2_BASE_ADDR:
518 ret = !gpio_get_value(USDHC2_CD_GPIO);
519 break;
520 case USDHC3_BASE_ADDR:
521 /*
522 * eMMC don't have card detect pin - since it is soldered to the
523 * PCB board
524 */
525 ret = 1;
526 break;
527 }
528 return ret;
529 }
530
board_mmc_init(struct bd_info * bis)531 int board_mmc_init(struct bd_info *bis)
532 {
533 int ret;
534 u32 index = 0;
535
536 /*
537 * MMC MAP
538 * (U-Boot device node) (Physical Port)
539 * mmc0 Soldered on board eMMC device
540 * mmc1 MicroSD card
541 */
542 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
543 switch (index) {
544 case 0:
545 SETUP_IOMUX_PADS(usdhc3_pads);
546 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
547 usdhc_cfg[0].max_bus_width = 8;
548 break;
549 case 1:
550 SETUP_IOMUX_PADS(usdhc2_pads);
551 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
552 usdhc_cfg[1].max_bus_width = 4;
553 gpio_direction_input(USDHC2_CD_GPIO);
554 break;
555 default:
556 printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
557 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
558 return -EINVAL;
559 }
560
561 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
562 if (ret)
563 return ret;
564 }
565
566 return 0;
567 }
568
569 #ifdef CONFIG_SPL_BOARD_INIT
570 #define DISPLAY_EN IMX_GPIO_NR(1, 2)
spl_board_init(void)571 void spl_board_init(void)
572 {
573 setup_eimnor();
574
575 gpio_direction_output(DISPLAY_EN, 1);
576 }
577 #endif /* CONFIG_SPL_BOARD_INIT */
578