1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2018
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
5 *
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux-vf610.h>
15 #include <asm/arch/ddrmc-vf610.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/clock.h>
18 #include <env.h>
19 #include <led.h>
20 #include <miiphy.h>
21 #include <linux/bitops.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
26 /* not in the datasheets, but in the original code */
27 { 0x00002000, 105 },
28 { 0x00000020, 110 },
29 /* AXI */
30 { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
31 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
32 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
33 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
34 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
35 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
36 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
37 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
38 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
39 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
40 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
41 { DDRMC_CR126_PHY_RDLAT(11), 126 },
42 { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
43 { DDRMC_CR137_PHYCTL_DL(2), 137 },
44 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
45 DDRMC_CR139_PHY_WRLV_DLL(3) |
46 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
47 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
48 DDRMC_CR154_PAD_ZQ_MODE(1) |
49 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
50 DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
51 { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
52 { DDRMC_CR158_TWR(6), 158 },
53 { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
54 DDRMC_CR161_TODTH_WR(6), 161 },
55 /* end marker */
56 { 0, -1 }
57 };
58
59 /* PHY settings -- most of them differ from default in imx-regs.h */
60
61 #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
62 #define PCM052_DDRMC_PHY_CTRL 0x00290000
63 #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
64 #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
65
66 static struct ddrmc_phy_setting pcm052_phy_settings[] = {
67 { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
68 { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
69 { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
70 { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
71 { DDRMC_PHY_DQS_TIMING, 1 },
72 { DDRMC_PHY_DQS_TIMING, 17 },
73 { DDRMC_PHY_DQS_TIMING, 33 },
74 { DDRMC_PHY_DQS_TIMING, 49 },
75 { PCM052_DDRMC_PHY_CTRL, 2 },
76 { PCM052_DDRMC_PHY_CTRL, 18 },
77 { PCM052_DDRMC_PHY_CTRL, 34 },
78 { DDRMC_PHY_MASTER_CTRL, 3 },
79 { DDRMC_PHY_MASTER_CTRL, 19 },
80 { DDRMC_PHY_MASTER_CTRL, 35 },
81 { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
82 { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
83 { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
84 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
85 { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
86
87 /* end marker */
88 { 0, -1 }
89 };
90
dram_init(void)91 int dram_init(void)
92 {
93 #if defined(CONFIG_TARGET_PCM052)
94
95 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
96 .tinit = 5,
97 .trst_pwron = 80000,
98 .cke_inactive = 200000,
99 .wrlat = 5,
100 .caslat_lin = 12,
101 .trc = 6,
102 .trrd = 4,
103 .tccd = 4,
104 .tbst_int_interval = 4,
105 .tfaw = 18,
106 .trp = 6,
107 .twtr = 4,
108 .tras_min = 15,
109 .tmrd = 4,
110 .trtp = 4,
111 .tras_max = 14040,
112 .tmod = 12,
113 .tckesr = 4,
114 .tcke = 3,
115 .trcd_int = 6,
116 .tras_lockout = 1,
117 .tdal = 10,
118 .bstlen = 3,
119 .tdll = 512,
120 .trp_ab = 6,
121 .tref = 1542,
122 .trfc = 64,
123 .tref_int = 5,
124 .tpdex = 3,
125 .txpdll = 10,
126 .txsnr = 68,
127 .txsr = 506,
128 .cksrx = 5,
129 .cksre = 5,
130 .freq_chg_en = 1,
131 .zqcl = 256,
132 .zqinit = 512,
133 .zqcs = 64,
134 .ref_per_zq = 64,
135 .zqcs_rotate = 1,
136 .aprebit = 10,
137 .cmd_age_cnt = 255,
138 .age_cnt = 255,
139 .q_fullness = 0,
140 .odt_rd_mapcs0 = 1,
141 .odt_wr_mapcs0 = 1,
142 .wlmrd = 40,
143 .wldqsen = 25,
144 };
145
146 const int row_diff = 2;
147
148 #elif defined(CONFIG_TARGET_BK4R1)
149
150 static const struct ddr3_jedec_timings pcm052_ddr_timings = {
151 .tinit = 5,
152 .trst_pwron = 80000,
153 .cke_inactive = 200000,
154 .wrlat = 5,
155 .caslat_lin = 12,
156 .trc = 6,
157 .trrd = 4,
158 .tccd = 4,
159 .tbst_int_interval = 0,
160 .tfaw = 16,
161 .trp = 6,
162 .twtr = 4,
163 .tras_min = 15,
164 .tmrd = 4,
165 .trtp = 4,
166 .tras_max = 28080,
167 .tmod = 12,
168 .tckesr = 4,
169 .tcke = 3,
170 .trcd_int = 6,
171 .tras_lockout = 1,
172 .tdal = 12,
173 .bstlen = 3,
174 .tdll = 512,
175 .trp_ab = 6,
176 .tref = 3120,
177 .trfc = 104,
178 .tref_int = 0,
179 .tpdex = 3,
180 .txpdll = 10,
181 .txsnr = 108,
182 .txsr = 512,
183 .cksrx = 5,
184 .cksre = 5,
185 .freq_chg_en = 1,
186 .zqcl = 256,
187 .zqinit = 512,
188 .zqcs = 64,
189 .ref_per_zq = 64,
190 .zqcs_rotate = 1,
191 .aprebit = 10,
192 .cmd_age_cnt = 255,
193 .age_cnt = 255,
194 .q_fullness = 0,
195 .odt_rd_mapcs0 = 1,
196 .odt_wr_mapcs0 = 1,
197 .wlmrd = 40,
198 .wldqsen = 25,
199 };
200
201 const int row_diff = 1;
202
203 #else /* Unknown PCM052 variant */
204
205 #error DDR characteristics undefined for this target. Please define them.
206
207 #endif
208
209 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
210 pcm052_phy_settings, 1, row_diff);
211
212 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
213
214 return 0;
215 }
216
clock_init(void)217 static void clock_init(void)
218 {
219 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
220 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
221
222 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
223 CCM_CCGR0_UART1_CTRL_MASK);
224 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
225 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
226 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
227 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
228 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
229 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
230 CCM_CCGR2_QSPI0_CTRL_MASK);
231 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
232 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
233 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
234 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
235 CCM_CCGR4_GPC_CTRL_MASK);
236 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
237 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
238 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
239 CCM_CCGR7_SDHC1_CTRL_MASK);
240 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
241 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
242 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
243 CCM_CCGR10_NFC_CTRL_MASK);
244
245 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
246 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
247 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
248 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
249
250 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
251 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
252 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
253 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
254 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
255 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
256 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
257 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
258 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
259 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
260 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
261 CCM_CACRR_ARM_CLK_DIV(0));
262 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
263 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
264 CCM_CSCMR1_QSPI0_CLK_SEL(3) |
265 CCM_CSCMR1_NFC_CLK_SEL(0));
266 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
267 CCM_CSCDR1_RMII_CLK_EN);
268 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
269 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
270 CCM_CSCDR2_NFC_EN);
271 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
272 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
273 CCM_CSCDR3_QSPI0_X2_DIV(1) |
274 CCM_CSCDR3_QSPI0_X4_DIV(3) |
275 CCM_CSCDR3_NFC_PRE_DIV(5));
276 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
277 CCM_CSCMR2_RMII_CLK_SEL(0));
278 }
279
mscm_init(void)280 static void mscm_init(void)
281 {
282 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
283 int i;
284
285 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
286 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
287 }
288
board_early_init_f(void)289 int board_early_init_f(void)
290 {
291 clock_init();
292 mscm_init();
293
294 return 0;
295 }
296
board_init(void)297 int board_init(void)
298 {
299 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
300
301 /* address of boot parameters */
302 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
303
304 /*
305 * Enable external 32K Oscillator
306 *
307 * The internal clock experiences significant drift
308 * so we must use the external oscillator in order
309 * to maintain correct time in the hwclock
310 */
311 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
312
313 return 0;
314 }
315
316 #ifdef CONFIG_TARGET_BK4R1
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)317 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
318 {
319 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
320 struct fuse_bank *bank = &ocotp->bank[4];
321 struct fuse_bank4_regs *fuse =
322 (struct fuse_bank4_regs *)bank->fuse_regs;
323 u32 value;
324
325 /*
326 * BK4 has different layout of stored MAC address
327 * than one used in imx_get_mac_from_fuse() @ generic.c
328 */
329
330 switch (dev_id) {
331 case 0:
332 value = readl(&fuse->mac_addr1);
333
334 mac[0] = value >> 8;
335 mac[1] = value;
336
337 value = readl(&fuse->mac_addr0);
338 mac[2] = value >> 24;
339 mac[3] = value >> 16;
340 mac[4] = value >> 8;
341 mac[5] = value;
342 break;
343 case 1:
344 value = readl(&fuse->mac_addr2);
345
346 mac[0] = value >> 24;
347 mac[1] = value >> 16;
348 mac[2] = value >> 8;
349 mac[3] = value;
350
351 value = readl(&fuse->mac_addr1);
352 mac[4] = value >> 24;
353 mac[5] = value >> 16;
354 break;
355 }
356 }
357
board_late_init(void)358 int board_late_init(void)
359 {
360 struct src *psrc = (struct src *)SRC_BASE_ADDR;
361 u32 reg;
362
363 if (IS_ENABLED(CONFIG_LED))
364 led_default_state();
365
366 /*
367 * BK4r1 handle emergency/service SD card boot
368 * Checking the SBMR1 register BOOTCFG1 byte:
369 * NAND:
370 * bit [2] - NAND data width - 16
371 * bit [5] - NAND fast boot
372 * bit [7] = 1 - NAND as a source of booting
373 * SD card (0x64):
374 * bit [4] = 0 - SD card source
375 * bit [6] = 1 - SD/MMC source
376 */
377
378 reg = readl(&psrc->sbmr1);
379 if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
380 !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
381 printf("------ SD card boot -------\n");
382 env_set_default("!LVFBootloader", 0);
383 env_set("bootcmd",
384 "run prepare_install_bk4r1_envs; run install_bk4r1rs");
385 }
386
387 return 0;
388 }
389
390 /**
391 * KSZ8081
392 */
393 #define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
394 #define RMII_50MHz_CLOCK 0x8180
395
board_phy_config(struct phy_device * phydev)396 int board_phy_config(struct phy_device *phydev)
397 {
398 /* Set 50 MHz reference clock */
399 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
400 RMII_50MHz_CLOCK);
401
402 return genphy_config(phydev);
403 }
404 #endif /* CONFIG_TARGET_BK4R1 */
405
checkboard(void)406 int checkboard(void)
407 {
408 #ifdef CONFIG_TARGET_BK4R1
409 u32 *gpio3_pdir = (u32 *)(GPIO3_BASE_ADDR + 0x10);
410
411 /*
412 * USB_RESET_N (PTC30 - GPIO103 - PORT3[7]):
413 * L333 -> pull up added -> read 1
414 * L320 -> no pull up -> read 0
415 *
416 * Default iomuxc_ptc30 value after reset: 0x300061 -> RCON28
417 * - input enabled, pull (up/down) disabled
418 */
419 if (*gpio3_pdir & BIT(7))
420 puts("Board: BK4r1 (L333)\n");
421 else
422 puts("Board: BK4r1 (L320)\n");
423 #else
424 puts("Board: PCM-052\n");
425 #endif
426 return 0;
427 }
428