1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/io.h>
9 #include <asm/addrspace.h>
10 #include <asm/types.h>
11 #include <mach/ar71xx_regs.h>
12 #include <mach/ddr.h>
13 #include <mach/ath79.h>
14 #include <debug_uart.h>
15
16 #define RST_RESET_RTC_RESET_LSB 27
17 #define RST_RESET_RTC_RESET_MASK 0x08000000
18 #define RST_RESET_RTC_RESET_SET(x) \
19 (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
20
21 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)22 void board_debug_uart_init(void)
23 {
24 void __iomem *regs;
25 u32 val;
26
27 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
28 MAP_NOCACHE);
29
30 /* UART : RX18, TX22 done
31 * GPIO18 as input, GPIO22 as output
32 */
33 val = readl(regs + AR71XX_GPIO_REG_OE);
34 val |= QCA956X_GPIO(18);
35 val &= ~QCA956X_GPIO(22);
36 writel(val, regs + AR71XX_GPIO_REG_OE);
37
38 /*
39 * Enable GPIO22 as UART0_SOUT
40 */
41 val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5);
42 val &= ~QCA956X_GPIO_MUX_MASK(16);
43 val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16;
44 writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5);
45
46 /*
47 * Enable GPIO18 as UART0_SIN
48 */
49 val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0);
50 val &= ~QCA956X_GPIO_MUX_MASK(8);
51 val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8;
52 writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0);
53
54 /*
55 * Enable GPIO22 output
56 */
57 val = readl(regs + AR71XX_GPIO_REG_OUT);
58 val |= QCA956X_GPIO(22);
59 writel(val, regs + AR71XX_GPIO_REG_OUT);
60 }
61 #endif
62
board_early_init_f(void)63 int board_early_init_f(void)
64 {
65 u32 reg;
66 void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
67 AR71XX_RESET_SIZE, MAP_NOCACHE);
68
69 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
70 /* CPU:775, DDR:650, AHB:258 */
71 qca956x_pll_init();
72 qca956x_ddr_init();
73 #endif
74
75 /* Take WMAC out of reset */
76 reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE);
77 reg &= (~RST_RESET_RTC_RESET_SET(1));
78 writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE);
79
80 ath79_eth_reset();
81 return 0;
82 }
83