1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout_spl.c
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <dm/platform_data/serial_sh.h>
13 #include <asm/processor.h>
14 #include <asm/mach-types.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include <linux/errno.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/rmobile.h>
21 #include <asm/arch/rcar-mstp.h>
22
23 #include <spl.h>
24
25 #define TMU0_MSTP125 BIT(25)
26 #define SCIFA0_MSTP204 BIT(4)
27 #define QSPI_MSTP917 BIT(17)
28
29 #define SD2CKCR 0xE615026C
30 #define SD_97500KHZ 0x7
31
32 struct reg_config {
33 u16 off;
34 u32 val;
35 };
36
dbsc_wait(u16 reg)37 static void dbsc_wait(u16 reg)
38 {
39 static const u32 dbsc3_0_base = DBSC3_0_BASE;
40 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
41
42 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
43 ;
44
45 while (!(readl(dbsc3_1_base + reg) & BIT(0)))
46 ;
47 }
48
spl_init_sys(void)49 static void spl_init_sys(void)
50 {
51 u32 r0 = 0;
52
53 writel(0xa5a5a500, 0xe6020004);
54 writel(0xa5a5a500, 0xe6030004);
55
56 asm volatile(
57 /* ICIALLU - Invalidate I$ to PoU */
58 "mcr 15, 0, %0, cr7, cr5, 0 \n"
59 /* BPIALL - Invalidate branch predictors */
60 "mcr 15, 0, %0, cr7, cr5, 6 \n"
61 /* Set SCTLR[IZ] */
62 "mrc 15, 0, %0, cr1, cr0, 0 \n"
63 "orr %0, #0x1800 \n"
64 "mcr 15, 0, %0, cr1, cr0, 0 \n"
65 "isb sy \n"
66 :"=r"(r0));
67 }
68
spl_init_pfc(void)69 static void spl_init_pfc(void)
70 {
71 static const struct reg_config pfc_with_unlock[] = {
72 { 0x0090, 0x00140300 },
73 { 0x0094, 0x09500000 },
74 { 0x0098, 0xc0000084 },
75 { 0x0020, 0x01a33492 },
76 { 0x0024, 0x10000000 },
77 { 0x0028, 0x08449252 },
78 { 0x002c, 0x2925b322 },
79 { 0x0030, 0x0c311249 },
80 { 0x0034, 0x10124000 },
81 { 0x0038, 0x00001295 },
82 { 0x003c, 0x50890000 },
83 { 0x0040, 0x0eaa56aa },
84 { 0x0044, 0x55550000 },
85 { 0x0048, 0x00000005 },
86 { 0x004c, 0x54800000 },
87 { 0x0050, 0x3736db55 },
88 { 0x0054, 0x29148da3 },
89 { 0x0058, 0x48c446e1 },
90 { 0x005c, 0x2a3a54dc },
91 { 0x0160, 0x00000023 },
92 { 0x0004, 0xfca0ffff },
93 { 0x0008, 0x3fbffbf0 },
94 { 0x000c, 0x3ffdffff },
95 { 0x0010, 0x00ffffff },
96 { 0x0014, 0xfc3ffff3 },
97 { 0x0018, 0xe4fdfff7 },
98 };
99
100 static const struct reg_config pfc_without_unlock[] = {
101 { 0x0104, 0xffffbfff },
102 { 0x0108, 0xb1ffffe1 },
103 { 0x010c, 0xffffffff },
104 { 0x0110, 0xffffffff },
105 { 0x0114, 0xe047beab },
106 { 0x0118, 0x00000203 },
107 };
108
109 static const u32 pfc_base = 0xe6060000;
110
111 unsigned int i;
112
113 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
114 writel(~pfc_with_unlock[i].val, pfc_base);
115 writel(pfc_with_unlock[i].val,
116 pfc_base | pfc_with_unlock[i].off);
117 }
118
119 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
120 writel(pfc_without_unlock[i].val,
121 pfc_base | pfc_without_unlock[i].off);
122 }
123
spl_init_gpio(void)124 static void spl_init_gpio(void)
125 {
126 static const u16 gpio_offs[] = {
127 0x1000, 0x3000, 0x4000, 0x5000
128 };
129
130 static const struct reg_config gpio_set[] = {
131 { 0x4000, 0x00c00000 },
132 { 0x5000, 0x63020000 },
133 };
134
135 static const struct reg_config gpio_clr[] = {
136 { 0x1000, 0x00000000 },
137 { 0x3000, 0x00000000 },
138 { 0x4000, 0x00c00000 },
139 { 0x5000, 0xe3020000 },
140 };
141
142 static const u32 gpio_base = 0xe6050000;
143
144 unsigned int i;
145
146 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
147 writel(0, gpio_base | 0x20 | gpio_offs[i]);
148
149 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
150 writel(0, gpio_base | 0x00 | gpio_offs[i]);
151
152 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
153 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
154
155 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
156 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
157 }
158
spl_init_lbsc(void)159 static void spl_init_lbsc(void)
160 {
161 static const struct reg_config lbsc_config[] = {
162 { 0x00, 0x00000020 },
163 { 0x08, 0x00002020 },
164 { 0x30, 0x02150326 },
165 { 0x38, 0x077f077f },
166 };
167
168 static const u16 lbsc_offs[] = {
169 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
170 };
171
172 static const u32 lbsc_base = 0xfec00200;
173
174 unsigned int i;
175
176 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
177 writel(lbsc_config[i].val,
178 lbsc_base | lbsc_config[i].off);
179 writel(lbsc_config[i].val,
180 lbsc_base | (lbsc_config[i].off + 4));
181 }
182
183 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
184 writel(0, lbsc_base | lbsc_offs[i]);
185 }
186
spl_init_dbsc(void)187 static void spl_init_dbsc(void)
188 {
189 static const struct reg_config dbsc_config1[] = {
190 { 0x0280, 0x0000a55a },
191 { 0x0018, 0x21000000 },
192 { 0x0018, 0x11000000 },
193 { 0x0018, 0x10000000 },
194 { 0x0290, 0x00000001 },
195 { 0x02a0, 0x80000000 },
196 { 0x0290, 0x00000004 },
197 };
198
199 static const struct reg_config dbsc_config2[] = {
200 { 0x0290, 0x00000006 },
201 { 0x02a0, 0x0001c000 },
202 };
203
204 static const struct reg_config dbsc_config3r0d0[] = {
205 { 0x0290, 0x0000000f },
206 { 0x02a0, 0x00181885 },
207 { 0x0290, 0x00000070 },
208 { 0x02a0, 0x7c000887 },
209 { 0x0290, 0x00000080 },
210 { 0x02a0, 0x7c000887 },
211 { 0x0290, 0x00000090 },
212 { 0x02a0, 0x7c000887 },
213 { 0x0290, 0x000000a0 },
214 { 0x02a0, 0x7c000887 },
215 { 0x0290, 0x000000b0 },
216 { 0x02a0, 0x7c000880 },
217 { 0x0290, 0x000000c0 },
218 { 0x02a0, 0x7c000880 },
219 { 0x0290, 0x000000d0 },
220 { 0x02a0, 0x7c000880 },
221 { 0x0290, 0x000000e0 },
222 { 0x02a0, 0x7c000880 },
223 };
224
225 static const struct reg_config dbsc_config3r0d1[] = {
226 { 0x0290, 0x0000000f },
227 { 0x02a0, 0x00181885 },
228 { 0x0290, 0x00000070 },
229 { 0x02a0, 0x7c000887 },
230 { 0x0290, 0x00000080 },
231 { 0x02a0, 0x7c000887 },
232 { 0x0290, 0x00000090 },
233 { 0x02a0, 0x7c000887 },
234 { 0x0290, 0x000000a0 },
235 { 0x02a0, 0x7c000887 },
236 };
237
238 static const struct reg_config dbsc_config3r2[] = {
239 { 0x0290, 0x0000000f },
240 { 0x02a0, 0x00181224 },
241 };
242
243 static const struct reg_config dbsc_config4[] = {
244 { 0x0290, 0x00000010 },
245 { 0x02a0, 0xf004649b },
246 { 0x0290, 0x00000061 },
247 { 0x02a0, 0x0000006d },
248 { 0x0290, 0x00000001 },
249 { 0x02a0, 0x00000073 },
250 { 0x0020, 0x00000007 },
251 { 0x0024, 0x0f030a02 },
252 { 0x0030, 0x00000001 },
253 { 0x00b0, 0x00000000 },
254 { 0x0040, 0x0000000b },
255 { 0x0044, 0x00000008 },
256 { 0x0048, 0x00000000 },
257 { 0x0050, 0x0000000b },
258 { 0x0054, 0x000c000b },
259 { 0x0058, 0x00000027 },
260 { 0x005c, 0x0000001c },
261 { 0x0060, 0x00000006 },
262 { 0x0064, 0x00000020 },
263 { 0x0068, 0x00000008 },
264 { 0x006c, 0x0000000c },
265 { 0x0070, 0x00000009 },
266 { 0x0074, 0x00000012 },
267 { 0x0078, 0x000000d0 },
268 { 0x007c, 0x00140005 },
269 { 0x0080, 0x00050004 },
270 { 0x0084, 0x70233005 },
271 { 0x0088, 0x000c0000 },
272 { 0x008c, 0x00000200 },
273 { 0x0090, 0x00000040 },
274 { 0x0100, 0x00000001 },
275 { 0x00c0, 0x00020001 },
276 { 0x00c8, 0x20042004 },
277 { 0x0380, 0x00020002 },
278 { 0x0390, 0x0000001f },
279 };
280
281 static const struct reg_config dbsc_config5[] = {
282 { 0x0244, 0x00000011 },
283 { 0x0290, 0x00000003 },
284 { 0x02a0, 0x0300c4e1 },
285 { 0x0290, 0x00000023 },
286 { 0x02a0, 0x00fcdb60 },
287 { 0x0290, 0x00000011 },
288 { 0x02a0, 0x1000040b },
289 { 0x0290, 0x00000012 },
290 { 0x02a0, 0x9d9cbb66 },
291 { 0x0290, 0x00000013 },
292 { 0x02a0, 0x1a868400 },
293 { 0x0290, 0x00000014 },
294 { 0x02a0, 0x300214d8 },
295 { 0x0290, 0x00000015 },
296 { 0x02a0, 0x00000d70 },
297 { 0x0290, 0x00000016 },
298 { 0x02a0, 0x00000006 },
299 { 0x0290, 0x00000017 },
300 { 0x02a0, 0x00000018 },
301 { 0x0290, 0x0000001a },
302 { 0x02a0, 0x910035c7 },
303 { 0x0290, 0x00000004 },
304 };
305
306 static const struct reg_config dbsc_config6[] = {
307 { 0x0290, 0x00000001 },
308 { 0x02a0, 0x00000181 },
309 { 0x0018, 0x11000000 },
310 { 0x0290, 0x00000004 },
311 };
312
313 static const struct reg_config dbsc_config7[] = {
314 { 0x0290, 0x00000001 },
315 { 0x02a0, 0x0000fe01 },
316 { 0x0304, 0x00000000 },
317 { 0x00f4, 0x01004c20 },
318 { 0x00f8, 0x014000aa },
319 { 0x00e0, 0x00000140 },
320 { 0x00e4, 0x00081860 },
321 { 0x00e8, 0x00010000 },
322 { 0x0290, 0x00000004 },
323 };
324
325 static const struct reg_config dbsc_config8[] = {
326 { 0x0014, 0x00000001 },
327 { 0x0010, 0x00000001 },
328 { 0x0280, 0x00000000 },
329 };
330
331 static const u32 dbsc3_0_base = DBSC3_0_BASE;
332 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
333 static const u32 prr_base = 0xff000044;
334 const u16 prr_rev = readl(prr_base) & 0x7fff;
335 unsigned int i;
336
337 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
338 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
339 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
340 }
341
342 dbsc_wait(0x2a0);
343
344 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
345 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
346 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
347 }
348
349 if (prr_rev == 0x4500) {
350 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
351 writel(dbsc_config3r0d0[i].val,
352 dbsc3_0_base | dbsc_config3r0d0[i].off);
353 }
354 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
355 writel(dbsc_config3r0d1[i].val,
356 dbsc3_1_base | dbsc_config3r0d1[i].off);
357 }
358 } else if (prr_rev != 0x4510) {
359 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
360 writel(dbsc_config3r2[i].val,
361 dbsc3_0_base | dbsc_config3r2[i].off);
362 writel(dbsc_config3r2[i].val,
363 dbsc3_1_base | dbsc_config3r2[i].off);
364 }
365 }
366
367 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
368 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
369 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
370 }
371
372 dbsc_wait(0x240);
373
374 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
375 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
376 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
377 }
378
379 dbsc_wait(0x2a0);
380
381 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
382 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
383 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
384 }
385
386 dbsc_wait(0x2a0);
387
388 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
389 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
390 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
391 }
392
393 dbsc_wait(0x2a0);
394
395 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
396 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
397 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
398 }
399
400 }
401
spl_init_qspi(void)402 static void spl_init_qspi(void)
403 {
404 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
405
406 static const u32 qspi_base = 0xe6b10000;
407
408 writeb(0x08, qspi_base + 0x00);
409 writeb(0x00, qspi_base + 0x01);
410 writeb(0x06, qspi_base + 0x02);
411 writeb(0x01, qspi_base + 0x0a);
412 writeb(0x00, qspi_base + 0x0b);
413 writeb(0x00, qspi_base + 0x0c);
414 writeb(0x00, qspi_base + 0x0d);
415 writeb(0x00, qspi_base + 0x0e);
416
417 writew(0xe080, qspi_base + 0x10);
418
419 writeb(0xc0, qspi_base + 0x18);
420 writeb(0x00, qspi_base + 0x18);
421 writeb(0x00, qspi_base + 0x08);
422 writeb(0x48, qspi_base + 0x00);
423 }
424
board_init_f(ulong dummy)425 void board_init_f(ulong dummy)
426 {
427 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
428 mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
429
430 /*
431 * SD0 clock is set to 97.5MHz by default.
432 * Set SD2 to the 97.5MHz as well.
433 */
434 writel(SD_97500KHZ, SD2CKCR);
435
436 spl_init_sys();
437 spl_init_pfc();
438 spl_init_gpio();
439 spl_init_lbsc();
440 spl_init_dbsc();
441 spl_init_qspi();
442 }
443
spl_board_init(void)444 void spl_board_init(void)
445 {
446 /* UART clocks enabled and gd valid - init serial console */
447 preloader_console_init();
448 }
449
board_boot_order(u32 * spl_boot_list)450 void board_boot_order(u32 *spl_boot_list)
451 {
452 const u32 jtag_magic = 0x1337c0de;
453 const u32 load_magic = 0xb33fc0de;
454
455 /*
456 * If JTAG probe sets special word at 0xe6300020, then it must
457 * put U-Boot into RAM and SPL will start it from RAM.
458 */
459 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
460 printf("JTAG boot detected!\n");
461
462 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
463 ;
464
465 spl_boot_list[0] = BOOT_DEVICE_RAM;
466 spl_boot_list[1] = BOOT_DEVICE_NONE;
467
468 return;
469 }
470
471 /* Boot from SPI NOR with YMODEM UART fallback. */
472 spl_boot_list[0] = BOOT_DEVICE_SPI;
473 spl_boot_list[1] = BOOT_DEVICE_UART;
474 spl_boot_list[2] = BOOT_DEVICE_NONE;
475 }
476
reset_cpu(ulong addr)477 void reset_cpu(ulong addr)
478 {
479 }
480