1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sbc8349.c -- WindRiver SBC8349 board support.
4 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 *
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 */
9
10 #include <common.h>
11 #include <fdt_support.h>
12 #include <init.h>
13 #include <ioports.h>
14 #include <mpc83xx.h>
15 #include <asm/bitops.h>
16 #include <asm/global_data.h>
17 #include <asm/mpc8349_pci.h>
18 #include <i2c.h>
19 #include <spd_sdram.h>
20 #include <miiphy.h>
21 #if defined(CONFIG_OF_LIBFDT)
22 #include <linux/libfdt.h>
23 #endif
24 #include <linux/delay.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 int fixed_sdram(void);
29 void sdram_init(void);
30
31 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
32 void ddr_enable_ecc(unsigned int dram_size);
33 #endif
34
35 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)36 int board_early_init_f (void)
37 {
38 return 0;
39 }
40 #endif
41
42 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
43
dram_init(void)44 int dram_init(void)
45 {
46 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
47 u32 msize = 0;
48
49 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
50 return -1;
51
52 /* DDR SDRAM - Main SODIMM */
53 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
54 #if defined(CONFIG_SPD_EEPROM)
55 msize = spd_sdram();
56 #else
57 msize = fixed_sdram();
58 #endif
59 /*
60 * Initialize SDRAM if it is on local bus.
61 */
62 sdram_init();
63
64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
65 /*
66 * Initialize and enable DDR ECC.
67 */
68 ddr_enable_ecc(msize * 1024 * 1024);
69 #endif
70 /* set total bus SDRAM size(bytes) -- DDR */
71 gd->ram_size = msize * 1024 * 1024;
72
73 return 0;
74 }
75
76 #if !defined(CONFIG_SPD_EEPROM)
77 /*************************************************************************
78 * fixed sdram init -- doesn't use serial presence detect.
79 ************************************************************************/
fixed_sdram(void)80 int fixed_sdram(void)
81 {
82 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
83 u32 msize = CONFIG_SYS_DDR_SIZE;
84 u32 ddr_size = msize << 20; /* DDR size in bytes */
85 u32 ddr_size_log2 = __ilog2(msize);
86
87 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
88 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
89
90 #if (CONFIG_SYS_DDR_SIZE != 256)
91 #warning Currently any ddr size other than 256 is not supported
92 #endif
93
94 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
95 #warning Chip select bounds is only configurable in 16MB increments
96 #endif
97 im->ddr.csbnds[2].csbnds =
98 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
99 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
100 CSBNDS_EA_SHIFT) & CSBNDS_EA);
101 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
102
103 /* currently we use only one CS, so disable the other banks */
104 im->ddr.cs_config[0] = 0;
105 im->ddr.cs_config[1] = 0;
106 im->ddr.cs_config[3] = 0;
107
108 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
109 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
110
111 im->ddr.sdram_cfg =
112 SDRAM_CFG_SREN
113 #if defined(CONFIG_DDR_2T_TIMING)
114 | SDRAM_CFG_2T_EN
115 #endif
116 | SDRAM_CFG_SDRAM_TYPE_DDR1;
117 #if defined (CONFIG_DDR_32BIT)
118 /* for 32-bit mode burst length is 8 */
119 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
120 #endif
121 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
122
123 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
124 udelay(200);
125
126 /* enable DDR controller */
127 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
128 return msize;
129 }
130 #endif/*!CONFIG_SYS_SPD_EEPROM*/
131
132
checkboard(void)133 int checkboard (void)
134 {
135 puts("Board: Wind River SBC834x\n");
136 return 0;
137 }
138
139 /*
140 * if board is fitted with SDRAM
141 */
142 #if defined(CONFIG_SYS_BR2_PRELIM) \
143 && defined(CONFIG_SYS_OR2_PRELIM) \
144 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
145 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
146 /*
147 * Initialize SDRAM memory on the Local Bus.
148 */
149
sdram_init(void)150 void sdram_init(void)
151 {
152 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
153 volatile fsl_lbc_t *lbc = &immap->im_lbc;
154 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
155 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
156 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
157 LSDMR_WRC3 | LSDMR_CL3;
158
159 puts("\n SDRAM on Local Bus: ");
160 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
161
162 /*
163 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
164 */
165
166 /* setup mtrpt, lsrt and lbcr for LB bus */
167 lbc->lbcr = 0x00000000;
168 /* LB refresh timer prescal, 266MHz/32 */
169 lbc->mrtpr = 0x20000000;
170 /* LB sdram refresh timer, about 6us */
171 lbc->lsrt = 0x32000000;
172 asm("sync");
173
174 /*
175 * Configure the SDRAM controller Machine Mode Register.
176 */
177 /* 0x40636733; normal operation */
178 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
179
180 /* 0x68636733; precharge all the banks */
181 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
182 asm("sync");
183 *sdram_addr = 0xff;
184 udelay(100);
185
186 /* 0x48636733; auto refresh */
187 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
188 asm("sync");
189 /*1 times*/
190 *sdram_addr = 0xff;
191 udelay(100);
192 /*2 times*/
193 *sdram_addr = 0xff;
194 udelay(100);
195 /*3 times*/
196 *sdram_addr = 0xff;
197 udelay(100);
198 /*4 times*/
199 *sdram_addr = 0xff;
200 udelay(100);
201 /*5 times*/
202 *sdram_addr = 0xff;
203 udelay(100);
204 /*6 times*/
205 *sdram_addr = 0xff;
206 udelay(100);
207 /*7 times*/
208 *sdram_addr = 0xff;
209 udelay(100);
210 /*8 times*/
211 *sdram_addr = 0xff;
212 udelay(100);
213
214 /* 0x58636733; mode register write operation */
215 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
216 asm("sync");
217 *sdram_addr = 0xff;
218 udelay(100);
219
220 /* 0x40636733; normal operation */
221 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
222 asm("sync");
223 *sdram_addr = 0xff;
224 udelay(100);
225 }
226 #else
sdram_init(void)227 void sdram_init(void)
228 {
229 puts(" SDRAM on Local Bus: Disabled in config\n");
230 }
231 #endif
232
233 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)234 int ft_board_setup(void *blob, struct bd_info *bd)
235 {
236 ft_cpu_setup(blob, bd);
237 #ifdef CONFIG_PCI
238 ft_pci_setup(blob, bd);
239 #endif
240
241 return 0;
242 }
243 #endif
244