1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
5 * Joe Hamman joe.hamman@embeddedspecialties.com
6 *
7 * Copyright 2004 Freescale Semiconductor.
8 * Jeff Brown
9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 *
11 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 */
13
14 #include <common.h>
15 #include <command.h>
16 #include <init.h>
17 #include <log.h>
18 #include <pci.h>
19 #include <asm/global_data.h>
20 #include <asm/processor.h>
21 #include <asm/immap_86xx.h>
22 #include <asm/fsl_pci.h>
23 #include <fsl_ddr_sdram.h>
24 #include <asm/fsl_serdes.h>
25 #include <linux/delay.h>
26 #include <linux/libfdt.h>
27 #include <fdt_support.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 long int fixed_sdram (void);
32
board_early_init_f(void)33 int board_early_init_f (void)
34 {
35 return 0;
36 }
37
checkboard(void)38 int checkboard (void)
39 {
40 puts ("Board: Wind River SBC8641D\n");
41
42 return 0;
43 }
44
dram_init(void)45 int dram_init(void)
46 {
47 long dram_size = 0;
48
49 #if defined(CONFIG_SPD_EEPROM)
50 dram_size = fsl_ddr_sdram();
51 #else
52 dram_size = fixed_sdram ();
53 #endif
54
55 debug(" DDR: ");
56 gd->ram_size = dram_size;
57
58 return 0;
59 }
60
61 #if defined(CONFIG_SYS_DRAM_TEST)
testdram(void)62 int testdram(void)
63 {
64 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
65 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
66 uint *p;
67
68 puts ("SDRAM test phase 1:\n");
69 for (p = pstart; p < pend; p++)
70 *p = 0xaaaaaaaa;
71
72 for (p = pstart; p < pend; p++) {
73 if (*p != 0xaaaaaaaa) {
74 printf ("SDRAM test fails at: %08x\n", (uint) p);
75 return 1;
76 }
77 }
78
79 puts ("SDRAM test phase 2:\n");
80 for (p = pstart; p < pend; p++)
81 *p = 0x55555555;
82
83 for (p = pstart; p < pend; p++) {
84 if (*p != 0x55555555) {
85 printf ("SDRAM test fails at: %08x\n", (uint) p);
86 return 1;
87 }
88 }
89
90 puts ("SDRAM test passed.\n");
91 return 0;
92 }
93 #endif
94
95 #if !defined(CONFIG_SPD_EEPROM)
96 /*
97 * Fixed sdram init -- doesn't use serial presence detect.
98 */
fixed_sdram(void)99 long int fixed_sdram (void)
100 {
101 #if !defined(CONFIG_SYS_RAMBOOT)
102 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
103 volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
104
105 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
106 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
107 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
108 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
109 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
110 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
111 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
112 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
113 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
114 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
115 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
116 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
117 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
119 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
120 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
121 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
122 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
123 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
124 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
125
126 asm ("sync;isync");
127
128 udelay(500);
129
130 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
131 asm ("sync; isync");
132
133 udelay(500);
134 ddr = &immap->im_ddr2;
135
136 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
137 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
138 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
139 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
140 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
141 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
142 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
143 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
144 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
145 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
146 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
147 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
148 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
149 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
150 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
151 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
152 ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
153 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
154 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
155 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
156
157 asm ("sync;isync");
158
159 udelay(500);
160
161 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
162 asm ("sync; isync");
163
164 udelay(500);
165 #endif
166 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
167 }
168 #endif /* !defined(CONFIG_SPD_EEPROM) */
169
170 #if defined(CONFIG_PCI)
171 /*
172 * Initialize PCI Devices, report devices found.
173 */
174
pci_init_board(void)175 void pci_init_board(void)
176 {
177 fsl_pcie_init_board(0);
178 }
179 #endif /* CONFIG_PCI */
180
181
182 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)183 int ft_board_setup(void *blob, struct bd_info *bd)
184 {
185 ft_cpu_setup(blob, bd);
186
187 FT_FSL_PCI_SETUP;
188
189 return 0;
190 }
191 #endif
192
sbc8641d_reset_board(void)193 void sbc8641d_reset_board (void)
194 {
195 puts ("Resetting board....\n");
196 }
197
198 /*
199 * get_board_sys_clk
200 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
201 */
202
get_board_sys_clk(ulong dummy)203 unsigned long get_board_sys_clk (ulong dummy)
204 {
205 int i;
206 ulong val = 0;
207
208 i = 5;
209 i &= 0x07;
210
211 switch (i) {
212 case 0:
213 val = 33000000;
214 break;
215 case 1:
216 val = 40000000;
217 break;
218 case 2:
219 val = 50000000;
220 break;
221 case 3:
222 val = 66000000;
223 break;
224 case 4:
225 val = 83000000;
226 break;
227 case 5:
228 val = 100000000;
229 break;
230 case 6:
231 val = 134000000;
232 break;
233 case 7:
234 val = 166000000;
235 break;
236 }
237
238 return val;
239 }
240
board_reset(void)241 void board_reset(void)
242 {
243 #ifdef CONFIG_SYS_RESET_ADDRESS
244 ulong addr = CONFIG_SYS_RESET_ADDRESS;
245
246 /* flush and disable I/D cache */
247 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
248 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
249 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
250 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
251 __asm__ __volatile__ ("sync");
252 __asm__ __volatile__ ("mtspr 1008, 4");
253 __asm__ __volatile__ ("isync");
254 __asm__ __volatile__ ("sync");
255 __asm__ __volatile__ ("mtspr 1008, 5");
256 __asm__ __volatile__ ("isync");
257 __asm__ __volatile__ ("sync");
258
259 /*
260 * SRR0 has system reset vector, SRR1 has default MSR value
261 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
262 */
263 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
264 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
265 __asm__ __volatile__ ("mtspr 27, 4");
266 __asm__ __volatile__ ("rfi");
267 #endif
268 }
269