1 /*
2 * mux.c
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <common.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/mux.h>
20 #include <asm/io.h>
21 #include <i2c.h>
22 #include "../common/board_detect.h"
23 #include "board.h"
24
25 static struct module_pin_mux uart0_pin_mux[] = {
26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
28 {-1},
29 };
30
31 static struct module_pin_mux uart1_pin_mux[] = {
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
34 {-1},
35 };
36
37 static struct module_pin_mux uart2_pin_mux[] = {
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
40 {-1},
41 };
42
43 static struct module_pin_mux uart3_pin_mux[] = {
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
46 {-1},
47 };
48
49 static struct module_pin_mux uart4_pin_mux[] = {
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
52 {-1},
53 };
54
55 static struct module_pin_mux uart5_pin_mux[] = {
56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
58 {-1},
59 };
60
61 static struct module_pin_mux mmc0_pin_mux[] = {
62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
69 {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
70 {-1},
71 };
72
73 static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
74 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
75 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
76 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
77 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
78 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
79 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
80 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
81 {-1},
82 };
83
84 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
85 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
86 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
87 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
88 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
89 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
90 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
91 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
92 {-1},
93 };
94
95 static struct module_pin_mux mmc1_pin_mux[] = {
96 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
97 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
98 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
99 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
100 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
101 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
102 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
103 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
104 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
105 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
106 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
107 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
108 {-1},
109 };
110
111 static struct module_pin_mux i2c0_pin_mux[] = {
112 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
113 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
114 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
115 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
116 {-1},
117 };
118
119 static struct module_pin_mux i2c1_pin_mux[] = {
120 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
121 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
122 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
123 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
124 {-1},
125 };
126
127 static struct module_pin_mux spi0_pin_mux[] = {
128 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
129 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
130 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
131 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
132 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
133 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
134 {-1},
135 };
136
137 static struct module_pin_mux gpio0_7_pin_mux[] = {
138 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
139 {-1},
140 };
141
142 static struct module_pin_mux gpio0_18_pin_mux[] = {
143 {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
144 {-1},
145 };
146
147 static struct module_pin_mux rgmii1_pin_mux[] = {
148 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
149 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
150 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
151 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
152 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
153 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
154 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
155 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
156 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
157 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
158 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
159 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
160 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
161 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
162 {-1},
163 };
164
165 static struct module_pin_mux mii1_pin_mux[] = {
166 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
167 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
168 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
169 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
170 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
171 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
172 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
173 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
174 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
175 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
176 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
177 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
178 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
179 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
180 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
181 {-1},
182 };
183
184 static struct module_pin_mux rmii1_pin_mux[] = {
185 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
186 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
187 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
188 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
189 {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
190 {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
191 {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
192 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
193 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
194 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
195 {-1},
196 };
197
198 #ifdef CONFIG_MTD_RAW_NAND
199 static struct module_pin_mux nand_pin_mux[] = {
200 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
201 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
202 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
203 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
204 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
205 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
206 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
207 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
208 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
209 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
210 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
211 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
212 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
213 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
214 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
215 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
216 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
217 #endif
218 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
219 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
220 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
221 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
222 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
223 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
224 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
225 {-1},
226 };
227 #elif defined(CONFIG_NOR)
228 static struct module_pin_mux bone_norcape_pin_mux[] = {
229 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
230 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
231 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
232 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
233 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
234 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
235 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
236 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
237 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
238 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
239 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
240 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
241 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
242 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
243 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
244 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
245 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
246 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
247 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
248 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
249 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
250 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
251 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
252 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
253 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
254 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
255 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
256 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
257 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
258 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
259 {-1},
260 };
261 #endif
262
263 static struct module_pin_mux uart3_icev2_pin_mux[] = {
264 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
265 {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
266 {-1},
267 };
268
269 #if defined(CONFIG_NOR_BOOT)
enable_norboot_pin_mux(void)270 void enable_norboot_pin_mux(void)
271 {
272 configure_module_pin_mux(bone_norcape_pin_mux);
273 }
274 #endif
275
enable_uart0_pin_mux(void)276 void enable_uart0_pin_mux(void)
277 {
278 configure_module_pin_mux(uart0_pin_mux);
279 }
280
enable_uart1_pin_mux(void)281 void enable_uart1_pin_mux(void)
282 {
283 configure_module_pin_mux(uart1_pin_mux);
284 }
285
enable_uart2_pin_mux(void)286 void enable_uart2_pin_mux(void)
287 {
288 configure_module_pin_mux(uart2_pin_mux);
289 }
290
enable_uart3_pin_mux(void)291 void enable_uart3_pin_mux(void)
292 {
293 configure_module_pin_mux(uart3_pin_mux);
294 }
295
enable_uart4_pin_mux(void)296 void enable_uart4_pin_mux(void)
297 {
298 configure_module_pin_mux(uart4_pin_mux);
299 }
300
enable_uart5_pin_mux(void)301 void enable_uart5_pin_mux(void)
302 {
303 configure_module_pin_mux(uart5_pin_mux);
304 }
305
enable_i2c0_pin_mux(void)306 void enable_i2c0_pin_mux(void)
307 {
308 configure_module_pin_mux(i2c0_pin_mux);
309 }
310
311 /*
312 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
313 * different profiles. These profiles determine what peripherals are
314 * valid and need pinmux to be configured.
315 */
316 #define PROFILE_NONE 0x0
317 #define PROFILE_0 (1 << 0)
318 #define PROFILE_1 (1 << 1)
319 #define PROFILE_2 (1 << 2)
320 #define PROFILE_3 (1 << 3)
321 #define PROFILE_4 (1 << 4)
322 #define PROFILE_5 (1 << 5)
323 #define PROFILE_6 (1 << 6)
324 #define PROFILE_7 (1 << 7)
325 #define PROFILE_MASK 0x7
326 #define PROFILE_ALL 0xFF
327
328 /* CPLD registers */
329 #define I2C_CPLD_ADDR 0x35
330 #define CFG_REG 0x10
331
detect_daughter_board_profile(void)332 static unsigned short detect_daughter_board_profile(void)
333 {
334 unsigned short val;
335
336 #if !CONFIG_IS_ENABLED(DM_I2C)
337 if (i2c_probe(I2C_CPLD_ADDR))
338 return PROFILE_NONE;
339
340 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
341 return PROFILE_NONE;
342 #else
343 struct udevice *dev = NULL;
344 int rc;
345
346 rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
347 if (rc)
348 return PROFILE_NONE;
349 rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
350 if (rc)
351 return PROFILE_NONE;
352 #endif
353 return (1 << (val & PROFILE_MASK));
354 }
355
enable_board_pin_mux(void)356 void enable_board_pin_mux(void)
357 {
358 /* Do board-specific muxes. */
359 if (board_is_bone()) {
360 /* Beaglebone pinmux */
361 configure_module_pin_mux(mii1_pin_mux);
362 configure_module_pin_mux(mmc0_pin_mux);
363 #if defined(CONFIG_MTD_RAW_NAND)
364 configure_module_pin_mux(nand_pin_mux);
365 #elif defined(CONFIG_NOR)
366 configure_module_pin_mux(bone_norcape_pin_mux);
367 #else
368 configure_module_pin_mux(mmc1_pin_mux);
369 #endif
370 } else if (board_is_gp_evm()) {
371 /* General Purpose EVM */
372 unsigned short profile = detect_daughter_board_profile();
373 configure_module_pin_mux(rgmii1_pin_mux);
374 configure_module_pin_mux(mmc0_pin_mux);
375 /* In profile #2 i2c1 and spi0 conflict. */
376 if (profile & ~PROFILE_2)
377 configure_module_pin_mux(i2c1_pin_mux);
378 /* Profiles 2 & 3 don't have NAND */
379 #ifdef CONFIG_MTD_RAW_NAND
380 if (profile & ~(PROFILE_2 | PROFILE_3))
381 configure_module_pin_mux(nand_pin_mux);
382 #endif
383 else if (profile == PROFILE_2) {
384 configure_module_pin_mux(mmc1_pin_mux);
385 configure_module_pin_mux(spi0_pin_mux);
386 }
387 } else if (board_is_idk()) {
388 /* Industrial Motor Control (IDK) */
389 configure_module_pin_mux(mii1_pin_mux);
390 configure_module_pin_mux(mmc0_no_cd_pin_mux);
391 } else if (board_is_evm_sk()) {
392 /* Starter Kit EVM */
393 configure_module_pin_mux(i2c1_pin_mux);
394 configure_module_pin_mux(gpio0_7_pin_mux);
395 configure_module_pin_mux(rgmii1_pin_mux);
396 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
397 } else if (board_is_bone_lt()) {
398 if (board_is_bben()) {
399 /* SanCloud Beaglebone LT Enhanced pinmux */
400 configure_module_pin_mux(rgmii1_pin_mux);
401 } else {
402 /* Beaglebone LT pinmux */
403 configure_module_pin_mux(mii1_pin_mux);
404 }
405 /* Beaglebone LT pinmux */
406 configure_module_pin_mux(mmc0_pin_mux);
407 #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
408 configure_module_pin_mux(nand_pin_mux);
409 #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
410 configure_module_pin_mux(bone_norcape_pin_mux);
411 #else
412 configure_module_pin_mux(mmc1_pin_mux);
413 #endif
414 } else if (board_is_pb()) {
415 configure_module_pin_mux(mii1_pin_mux);
416 configure_module_pin_mux(mmc0_pin_mux);
417 } else if (board_is_icev2()) {
418 configure_module_pin_mux(mmc0_pin_mux);
419 configure_module_pin_mux(gpio0_18_pin_mux);
420 configure_module_pin_mux(uart3_icev2_pin_mux);
421 configure_module_pin_mux(rmii1_pin_mux);
422 configure_module_pin_mux(spi0_pin_mux);
423 } else {
424 /* Unknown board. We might still be able to boot. */
425 puts("Bad EEPROM or unknown board, cannot configure pinmux.");
426 }
427 }
428