1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 Toradex
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx8-pins.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/sci/sci.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/global_data.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <env.h>
19 #include <errno.h>
20 #include <linux/libfdt.h>
21
22 #include "../common/tdx-cfg-block.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
27 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
28 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
29 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
30
31 static iomux_cfg_t uart1_pads[] = {
32 SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
34 };
35
setup_iomux_uart(void)36 static void setup_iomux_uart(void)
37 {
38 imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
39 }
40
board_mem_get_layout(u64 * phys_sdram_1_start,u64 * phys_sdram_1_size,u64 * phys_sdram_2_start,u64 * phys_sdram_2_size)41 void board_mem_get_layout(u64 *phys_sdram_1_start,
42 u64 *phys_sdram_1_size,
43 u64 *phys_sdram_2_start,
44 u64 *phys_sdram_2_size)
45 {
46 u32 is_dualx = 0, val = 0;
47 sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
48
49 if (scierr == SC_ERR_NONE) {
50 /* DX has two A35 cores disabled */
51 is_dualx = (val & 0xf) != 0x0;
52 }
53
54 *phys_sdram_1_start = PHYS_SDRAM_1;
55 if (is_dualx)
56 /* Our DX based SKUs only have 1 GB RAM */
57 *phys_sdram_1_size = SZ_1G;
58 else
59 *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
60 *phys_sdram_2_start = PHYS_SDRAM_2;
61 *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
62 }
63
board_early_init_f(void)64 int board_early_init_f(void)
65 {
66 sc_pm_clock_rate_t rate;
67 sc_err_t err = 0;
68
69 /*
70 * This works around that having only UART3 up the baudrate is 1.2M
71 * instead of 115.2k. Set UART0 clock root to 80 MHz
72 */
73 rate = 80000000;
74 err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
75 if (err != SC_ERR_NONE)
76 return 0;
77
78 /* Set UART3 clock root to 80 MHz and enable it */
79 rate = SC_80MHZ;
80 err = sc_pm_setup_uart(SC_R_UART_1, rate);
81 if (err != SC_ERR_NONE)
82 return 0;
83
84 setup_iomux_uart();
85
86 return 0;
87 }
88
89 #if IS_ENABLED(CONFIG_DM_GPIO)
board_gpio_init(void)90 static void board_gpio_init(void)
91 {
92 /* TODO */
93 }
94 #else
board_gpio_init(void)95 static inline void board_gpio_init(void) {}
96 #endif
97
98 #if IS_ENABLED(CONFIG_FEC_MXC)
99 #include <miiphy.h>
100
board_phy_config(struct phy_device * phydev)101 int board_phy_config(struct phy_device *phydev)
102 {
103 if (phydev->drv->config)
104 phydev->drv->config(phydev);
105
106 return 0;
107 }
108 #endif
109
checkboard(void)110 int checkboard(void)
111 {
112 puts("Model: Toradex Apalis iMX8X\n");
113
114 build_info();
115 print_bootinfo();
116
117 return 0;
118 }
119
board_init(void)120 int board_init(void)
121 {
122 board_gpio_init();
123
124 return 0;
125 }
126
127 /*
128 * Board specific reset that is system reset.
129 */
reset_cpu(ulong addr)130 void reset_cpu(ulong addr)
131 {
132 /* TODO */
133 }
134
135 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)136 int ft_board_setup(void *blob, struct bd_info *bd)
137 {
138 return ft_common_board_setup(blob, bd);
139 }
140 #endif
141
board_mmc_get_env_dev(int devno)142 int board_mmc_get_env_dev(int devno)
143 {
144 return devno;
145 }
146
board_late_init(void)147 int board_late_init(void)
148 {
149 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
150 /* TODO move to common */
151 env_set("board_name", "Apalis iMX8X");
152 #endif
153
154 return 0;
155 }
156