1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 * Copyright (C) Jasbir Matharu
5 * Copyright (C) UDOO Team
6 *
7 * Author: Breno Lima <breno.lima@nxp.com>
8 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 */
10
11 #include <init.h>
12 #include <net.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/mx6-pins.h>
18 #include <asm/global_data.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <env.h>
22 #include <mmc.h>
23 #include <fsl_esdhc_imx.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h>
26 #include <asm/mach-imx/mxc_i2c.h>
27 #include <asm/arch/sys_proto.h>
28 #include <spl.h>
29 #include <linux/delay.h>
30 #include <linux/sizes.h>
31 #include <common.h>
32 #include <i2c.h>
33 #include <miiphy.h>
34 #include <netdev.h>
35 #include <power/pmic.h>
36 #include <power/pfuze3000_pmic.h>
37 #include <malloc.h>
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 enum {
42 UDOO_NEO_TYPE_BASIC,
43 UDOO_NEO_TYPE_BASIC_KS,
44 UDOO_NEO_TYPE_FULL,
45 UDOO_NEO_TYPE_EXTENDED,
46 };
47
48 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
53 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
54 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
57 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
58 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
59 PAD_CTL_ODE)
60
61 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
62 PAD_CTL_SPEED_MED | \
63 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
64
65 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
66 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
67
68 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
69 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
70
71 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
72 PAD_CTL_DSE_40ohm)
73
74 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
75 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
76 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
77 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
78 MUX_MODE_SION)
79
dram_init(void)80 int dram_init(void)
81 {
82 gd->ram_size = imx_ddr_size();
83 return 0;
84 }
85
86 #ifdef CONFIG_SYS_I2C_MXC
87 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
88 /* I2C1 for PMIC */
89 static struct i2c_pads_info i2c_pad_info1 = {
90 .scl = {
91 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
92 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
93 .gp = IMX_GPIO_NR(1, 0),
94 },
95 .sda = {
96 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
97 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
98 .gp = IMX_GPIO_NR(1, 1),
99 },
100 };
101 #endif
102
103 #ifdef CONFIG_POWER
power_init_board(void)104 int power_init_board(void)
105 {
106 struct pmic *p;
107 int ret;
108 unsigned int reg, rev_id;
109
110 ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
111 if (ret)
112 return ret;
113
114 p = pmic_get("PFUZE3000");
115 ret = pmic_probe(p);
116 if (ret)
117 return ret;
118
119 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
120 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
121 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
122
123 /* disable Low Power Mode during standby mode */
124 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
125 reg |= 0x1;
126 ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
127 if (ret)
128 return ret;
129
130 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
131 if (ret)
132 return ret;
133
134 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
135 if (ret)
136 return ret;
137
138 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
139 if (ret)
140 return ret;
141
142 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
143 if (ret)
144 return ret;
145
146 /* set SW1A standby voltage 0.975V */
147 pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
148 reg &= ~0x3f;
149 reg |= PFUZE3000_SW1AB_SETP(9750);
150 ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
151 if (ret)
152 return ret;
153
154 /* set SW1B standby voltage 0.975V */
155 pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
156 reg &= ~0x3f;
157 reg |= PFUZE3000_SW1AB_SETP(9750);
158 ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
159 if (ret)
160 return ret;
161
162 /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
163 pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
164 reg &= ~0xc0;
165 reg |= 0x40;
166 ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
167 if (ret)
168 return ret;
169
170 /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
171 pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
172 reg &= ~0xc0;
173 reg |= 0x40;
174 ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
175 if (ret)
176 return ret;
177
178 /* set VDD_ARM_IN to 1.350V */
179 pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
180 reg &= ~0x3f;
181 reg |= PFUZE3000_SW1AB_SETP(13500);
182 ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
183 if (ret)
184 return ret;
185
186 /* set VDD_SOC_IN to 1.350V */
187 pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
188 reg &= ~0x3f;
189 reg |= PFUZE3000_SW1AB_SETP(13500);
190 ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
191 if (ret)
192 return ret;
193
194 /* set DDR_1_5V to 1.350V */
195 pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
196 reg &= ~0x0f;
197 reg |= PFUZE3000_SW3_SETP(13500);
198 ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
199 if (ret)
200 return ret;
201
202 /* set VGEN2_1V5 to 1.5V */
203 pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
204 reg &= ~0x0f;
205 reg |= PFUZE3000_VLDO_SETP(15000);
206 /* enable */
207 reg |= 0x10;
208 ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
209 if (ret)
210 return ret;
211
212 return 0;
213 }
214 #endif
215
216 static iomux_v3_cfg_t const uart1_pads[] = {
217 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
218 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
219 };
220
221 static iomux_v3_cfg_t const usdhc2_pads[] = {
222 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
223 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
224 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
225 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
226 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
227 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
228 /* CD pin */
229 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
230 /* Power */
231 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
232 };
233
234 static iomux_v3_cfg_t const fec1_pads[] = {
235 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
238 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
239 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
240 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
242 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
243 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
244 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
245 MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
246 MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
247 };
248
249 static iomux_v3_cfg_t const phy_control_pads[] = {
250 /* 25MHz Ethernet PHY Clock */
251 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
252 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
253 };
254
255 static iomux_v3_cfg_t const board_recognition_pads[] = {
256 /*Connected to R184*/
257 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
258 /*Connected to R185*/
259 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
260 };
261
262 static iomux_v3_cfg_t const wdog_b_pad = {
263 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
264 };
265
266 static iomux_v3_cfg_t const peri_3v3_pads[] = {
267 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
268 };
269
setup_iomux_uart(void)270 static void setup_iomux_uart(void)
271 {
272 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
273 }
274
setup_fec(int fec_id)275 static int setup_fec(int fec_id)
276 {
277 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
278 int reg;
279
280 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
281 ARRAY_SIZE(phy_control_pads));
282
283 /* Reset PHY */
284 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
285 udelay(10000);
286 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
287 udelay(100);
288
289 reg = readl(&anatop->pll_enet);
290 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
291 writel(reg, &anatop->pll_enet);
292
293 return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
294 }
295
board_eth_init(struct bd_info * bis)296 int board_eth_init(struct bd_info *bis)
297 {
298 uint32_t base = IMX_FEC_BASE;
299 struct mii_dev *bus = NULL;
300 struct phy_device *phydev = NULL;
301 int ret;
302
303 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
304
305 setup_fec(CONFIG_FEC_ENET_DEV);
306
307 bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
308 if (!bus)
309 return -EINVAL;
310
311 phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
312 PHY_INTERFACE_MODE_RMII);
313 if (!phydev) {
314 free(bus);
315 return -EINVAL;
316 }
317
318 ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
319 if (ret) {
320 free(bus);
321 free(phydev);
322 return ret;
323 }
324 return 0;
325 }
326
board_phy_config(struct phy_device * phydev)327 int board_phy_config(struct phy_device *phydev)
328 {
329 if (phydev->drv->config)
330 phydev->drv->config(phydev);
331
332 return 0;
333 }
334
board_init(void)335 int board_init(void)
336 {
337 /* Address of boot parameters */
338 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
339
340 /*
341 * Because kernel set WDOG_B mux before pad with the commone pinctrl
342 * framwork now and wdog reset will be triggered once set WDOG_B mux
343 * with default pad setting, we set pad setting here to workaround this.
344 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
345 * as GPIO mux firstly here to workaround it.
346 */
347 imx_iomux_v3_setup_pad(wdog_b_pad);
348
349 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
350 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
351 ARRAY_SIZE(peri_3v3_pads));
352
353 /* Active high for ncp692 */
354 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
355
356 #ifdef CONFIG_SYS_I2C_MXC
357 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
358 #endif
359
360 return 0;
361 }
362
get_board_value(void)363 static int get_board_value(void)
364 {
365 int r184, r185;
366
367 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
368 ARRAY_SIZE(board_recognition_pads));
369
370 gpio_direction_input(IMX_GPIO_NR(4, 13));
371 gpio_direction_input(IMX_GPIO_NR(4, 0));
372
373 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
374 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
375
376 /*
377 * Machine selection -
378 * Machine r184, r185
379 * ---------------------------------
380 * Basic 0 0
381 * Basic Ks 0 1
382 * Full 1 0
383 * Extended 1 1
384 */
385
386 return (r184 << 1) + r185;
387 }
388
board_early_init_f(void)389 int board_early_init_f(void)
390 {
391 setup_iomux_uart();
392
393 return 0;
394 }
395
396 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
397 {USDHC2_BASE_ADDR, 0, 4},
398 };
399
400 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
401 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
402
board_mmc_getcd(struct mmc * mmc)403 int board_mmc_getcd(struct mmc *mmc)
404 {
405 return !gpio_get_value(USDHC2_CD_GPIO);
406 }
407
board_mmc_init(struct bd_info * bis)408 int board_mmc_init(struct bd_info *bis)
409 {
410 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
411 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
412 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
413 gpio_direction_input(USDHC2_CD_GPIO);
414 gpio_direction_output(USDHC2_PWR_GPIO, 1);
415
416 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
417 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
418 }
419
board_string(void)420 static char *board_string(void)
421 {
422 switch (get_board_value()) {
423 case UDOO_NEO_TYPE_BASIC:
424 return "BASIC";
425 case UDOO_NEO_TYPE_BASIC_KS:
426 return "BASICKS";
427 case UDOO_NEO_TYPE_FULL:
428 return "FULL";
429 case UDOO_NEO_TYPE_EXTENDED:
430 return "EXTENDED";
431 }
432 return "UNDEFINED";
433 }
434
checkboard(void)435 int checkboard(void)
436 {
437 printf("Board: UDOO Neo %s\n", board_string());
438 return 0;
439 }
440
board_late_init(void)441 int board_late_init(void)
442 {
443 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
444 env_set("board_name", board_string());
445 #endif
446
447 return 0;
448 }
449
450 #ifdef CONFIG_SPL_BUILD
451
452 #include <linux/libfdt.h>
453 #include <asm/arch/mx6-ddr.h>
454
455 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
456 .dram_dqm0 = 0x00000028,
457 .dram_dqm1 = 0x00000028,
458 .dram_dqm2 = 0x00000028,
459 .dram_dqm3 = 0x00000028,
460 .dram_ras = 0x00000020,
461 .dram_cas = 0x00000020,
462 .dram_odt0 = 0x00000020,
463 .dram_odt1 = 0x00000020,
464 .dram_sdba2 = 0x00000000,
465 .dram_sdcke0 = 0x00003000,
466 .dram_sdcke1 = 0x00003000,
467 .dram_sdclk_0 = 0x00000030,
468 .dram_sdqs0 = 0x00000028,
469 .dram_sdqs1 = 0x00000028,
470 .dram_sdqs2 = 0x00000028,
471 .dram_sdqs3 = 0x00000028,
472 .dram_reset = 0x00000020,
473 };
474
475 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
476 .grp_addds = 0x00000020,
477 .grp_ddrmode_ctl = 0x00020000,
478 .grp_ddrpke = 0x00000000,
479 .grp_ddrmode = 0x00020000,
480 .grp_b0ds = 0x00000028,
481 .grp_b1ds = 0x00000028,
482 .grp_ctlds = 0x00000020,
483 .grp_ddr_type = 0x000c0000,
484 .grp_b2ds = 0x00000028,
485 .grp_b3ds = 0x00000028,
486 };
487
488 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
489 .p0_mpwldectrl0 = 0x000E000B,
490 .p0_mpwldectrl1 = 0x000E0010,
491 .p0_mpdgctrl0 = 0x41600158,
492 .p0_mpdgctrl1 = 0x01500140,
493 .p0_mprddlctl = 0x3A383E3E,
494 .p0_mpwrdlctl = 0x3A383C38,
495 };
496
497 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
498 .p0_mpwldectrl0 = 0x001E0022,
499 .p0_mpwldectrl1 = 0x001C0019,
500 .p0_mpdgctrl0 = 0x41540150,
501 .p0_mpdgctrl1 = 0x01440138,
502 .p0_mprddlctl = 0x403E4644,
503 .p0_mpwrdlctl = 0x3C3A4038,
504 };
505
506 /* MT41K256M16 */
507 static struct mx6_ddr3_cfg neo_mem_ddr = {
508 .mem_speed = 1600,
509 .density = 4,
510 .width = 16,
511 .banks = 8,
512 .rowaddr = 15,
513 .coladdr = 10,
514 .pagesz = 2,
515 .trcd = 1375,
516 .trcmin = 4875,
517 .trasmin = 3500,
518 };
519
520 /* MT41K128M16 */
521 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
522 .mem_speed = 1600,
523 .density = 2,
524 .width = 16,
525 .banks = 8,
526 .rowaddr = 14,
527 .coladdr = 10,
528 .pagesz = 2,
529 .trcd = 1375,
530 .trcmin = 4875,
531 .trasmin = 3500,
532 };
533
ccgr_init(void)534 static void ccgr_init(void)
535 {
536 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
537
538 writel(0xFFFFFFFF, &ccm->CCGR0);
539 writel(0xFFFFFFFF, &ccm->CCGR1);
540 writel(0xFFFFFFFF, &ccm->CCGR2);
541 writel(0xFFFFFFFF, &ccm->CCGR3);
542 writel(0xFFFFFFFF, &ccm->CCGR4);
543 writel(0xFFFFFFFF, &ccm->CCGR5);
544 writel(0xFFFFFFFF, &ccm->CCGR6);
545 writel(0xFFFFFFFF, &ccm->CCGR7);
546 }
547
spl_dram_init(void)548 static void spl_dram_init(void)
549 {
550 int board = get_board_value();
551
552 struct mx6_ddr_sysinfo sysinfo = {
553 .dsize = 1, /* width of data bus: 1 = 32 bits */
554 .cs_density = 24,
555 .ncs = 1,
556 .cs1_mirror = 0,
557 .rtt_wr = 2,
558 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
559 .walat = 1, /* Write additional latency */
560 .ralat = 5, /* Read additional latency */
561 .mif3_mode = 3, /* Command prediction working mode */
562 .bi_on = 1, /* Bank interleaving enabled */
563 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
564 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
565 };
566
567 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
568 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
569 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
570 &neo_basic_mem_ddr);
571 else
572 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
573 }
574
board_init_f(ulong dummy)575 void board_init_f(ulong dummy)
576 {
577 ccgr_init();
578
579 /* setup AIPS and disable watchdog */
580 arch_cpu_init();
581
582 board_early_init_f();
583
584 /* setup GP timer */
585 timer_init();
586
587 /* UART clocks enabled and gd valid - init serial console */
588 preloader_console_init();
589
590 /* DDR initialization */
591 spl_dram_init();
592
593 /* Clear the BSS. */
594 memset(__bss_start, 0, __bss_end - __bss_start);
595
596 /* load/boot image from boot device */
597 board_init_r(NULL, 0);
598 }
599
600 #endif
601