1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <env.h>
10 #include <fdtdec.h>
11 #include <init.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <time.h>
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/sys_proto.h>
20 #include <dm/device.h>
21 #include <dm/uclass.h>
22 #include <versalpl.h>
23 #include "../common/board.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #if defined(CONFIG_FPGA_VERSALPL)
28 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
29 #endif
30
board_init(void)31 int board_init(void)
32 {
33 printf("EL Level:\tEL%d\n", current_el());
34
35 #if defined(CONFIG_FPGA_VERSALPL)
36 fpga_init();
37 fpga_add(fpga_xilinx, &versalpl);
38 #endif
39
40 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
41 xilinx_read_eeprom();
42
43 return 0;
44 }
45
board_early_init_r(void)46 int board_early_init_r(void)
47 {
48 u32 val;
49
50 if (current_el() != 3)
51 return 0;
52
53 debug("iou_switch ctrl div0 %x\n",
54 readl(&crlapb_base->iou_switch_ctrl));
55
56 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
57 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
58 &crlapb_base->iou_switch_ctrl);
59
60 /* Global timer init - Program time stamp reference clk */
61 val = readl(&crlapb_base->timestamp_ref_ctrl);
62 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
63 writel(val, &crlapb_base->timestamp_ref_ctrl);
64
65 debug("ref ctrl 0x%x\n",
66 readl(&crlapb_base->timestamp_ref_ctrl));
67
68 /* Clear reset of timestamp reg */
69 writel(0, &crlapb_base->rst_timestamp);
70
71 /*
72 * Program freq register in System counter and
73 * enable system counter.
74 */
75 writel(COUNTER_FREQUENCY,
76 &iou_scntr_secure->base_frequency_id_register);
77
78 debug("counter val 0x%x\n",
79 readl(&iou_scntr_secure->base_frequency_id_register));
80
81 writel(IOU_SCNTRS_CONTROL_EN,
82 &iou_scntr_secure->counter_control_register);
83
84 debug("scntrs control 0x%x\n",
85 readl(&iou_scntr_secure->counter_control_register));
86 debug("timer 0x%llx\n", get_ticks());
87 debug("timer 0x%llx\n", get_ticks());
88
89 return 0;
90 }
91
versal_get_bootmode(void)92 static u8 versal_get_bootmode(void)
93 {
94 u8 bootmode;
95 u32 reg = 0;
96
97 reg = readl(&crp_base->boot_mode_usr);
98
99 if (reg >> BOOT_MODE_ALT_SHIFT)
100 reg >>= BOOT_MODE_ALT_SHIFT;
101
102 bootmode = reg & BOOT_MODES_MASK;
103
104 return bootmode;
105 }
106
board_late_init(void)107 int board_late_init(void)
108 {
109 u8 bootmode;
110 struct udevice *dev;
111 int bootseq = -1;
112 int bootseq_len = 0;
113 int env_targets_len = 0;
114 const char *mode;
115 char *new_targets;
116 char *env_targets;
117
118 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
119 debug("Saved variables - Skipping\n");
120 return 0;
121 }
122
123 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
124 return 0;
125
126 bootmode = versal_get_bootmode();
127
128 puts("Bootmode: ");
129 switch (bootmode) {
130 case USB_MODE:
131 puts("USB_MODE\n");
132 mode = "dfu_usb";
133 break;
134 case JTAG_MODE:
135 puts("JTAG_MODE\n");
136 mode = "jtag pxe dhcp";
137 break;
138 case QSPI_MODE_24BIT:
139 puts("QSPI_MODE_24\n");
140 mode = "xspi0";
141 break;
142 case QSPI_MODE_32BIT:
143 puts("QSPI_MODE_32\n");
144 mode = "xspi0";
145 break;
146 case OSPI_MODE:
147 puts("OSPI_MODE\n");
148 mode = "xspi0";
149 break;
150 case EMMC_MODE:
151 puts("EMMC_MODE\n");
152 if (uclass_get_device_by_name(UCLASS_MMC,
153 "sdhci@f1050000", &dev)) {
154 puts("Boot from EMMC but without SD1 enabled!\n");
155 return -1;
156 }
157 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
158 mode = "mmc";
159 bootseq = dev_seq(dev);
160 break;
161 case SD_MODE:
162 puts("SD_MODE\n");
163 if (uclass_get_device_by_name(UCLASS_MMC,
164 "sdhci@f1040000", &dev)) {
165 puts("Boot from SD0 but without SD0 enabled!\n");
166 return -1;
167 }
168 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
169
170 mode = "mmc";
171 bootseq = dev_seq(dev);
172 break;
173 case SD1_LSHFT_MODE:
174 puts("LVL_SHFT_");
175 /* fall through */
176 case SD_MODE1:
177 puts("SD_MODE1\n");
178 if (uclass_get_device_by_name(UCLASS_MMC,
179 "sdhci@f1050000", &dev)) {
180 puts("Boot from SD1 but without SD1 enabled!\n");
181 return -1;
182 }
183 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
184
185 mode = "mmc";
186 bootseq = dev_seq(dev);
187 break;
188 default:
189 mode = "";
190 printf("Invalid Boot Mode:0x%x\n", bootmode);
191 break;
192 }
193
194 if (bootseq >= 0) {
195 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
196 debug("Bootseq len: %x\n", bootseq_len);
197 }
198
199 /*
200 * One terminating char + one byte for space between mode
201 * and default boot_targets
202 */
203 env_targets = env_get("boot_targets");
204 if (env_targets)
205 env_targets_len = strlen(env_targets);
206
207 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
208 bootseq_len);
209 if (!new_targets)
210 return -ENOMEM;
211
212 if (bootseq >= 0)
213 sprintf(new_targets, "%s%x %s", mode, bootseq,
214 env_targets ? env_targets : "");
215 else
216 sprintf(new_targets, "%s %s", mode,
217 env_targets ? env_targets : "");
218
219 env_set("boot_targets", new_targets);
220
221 return board_late_init_xilinx();
222 }
223
dram_init_banksize(void)224 int dram_init_banksize(void)
225 {
226 int ret;
227
228 ret = fdtdec_setup_memory_banksize();
229 if (ret)
230 return ret;
231
232 mem_map_fill();
233
234 return 0;
235 }
236
dram_init(void)237 int dram_init(void)
238 {
239 if (fdtdec_setup_mem_size_base_lowest() != 0)
240 return -EINVAL;
241
242 return 0;
243 }
244
reset_cpu(ulong addr)245 void reset_cpu(ulong addr)
246 {
247 }
248