1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <dm/device-internal.h>
10 #include <linux/clk-provider.h>
11
clk_fixed_rate_get_rate(struct clk * clk)12 static ulong clk_fixed_rate_get_rate(struct clk *clk)
13 {
14 return to_clk_fixed_rate(clk->dev)->fixed_rate;
15 }
16
17 /* avoid clk_enable() return -ENOSYS */
dummy_enable(struct clk * clk)18 static int dummy_enable(struct clk *clk)
19 {
20 return 0;
21 }
22
23 const struct clk_ops clk_fixed_rate_ops = {
24 .get_rate = clk_fixed_rate_get_rate,
25 .enable = dummy_enable,
26 };
27
clk_fixed_rate_of_to_plat(struct udevice * dev)28 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
29 {
30 struct clk *clk = &to_clk_fixed_rate(dev)->clk;
31 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
32 to_clk_fixed_rate(dev)->fixed_rate =
33 dev_read_u32_default(dev, "clock-frequency", 0);
34 #endif
35 /* Make fixed rate clock accessible from higher level struct clk */
36 /* FIXME: This is not allowed */
37 dev_set_uclass_priv(dev, clk);
38 clk->dev = dev;
39 clk->enable_count = 0;
40
41 return 0;
42 }
43
44 static const struct udevice_id clk_fixed_rate_match[] = {
45 {
46 .compatible = "fixed-clock",
47 },
48 { /* sentinel */ }
49 };
50
51 U_BOOT_DRIVER(fixed_clock) = {
52 .name = "fixed_clock",
53 .id = UCLASS_CLK,
54 .of_match = clk_fixed_rate_match,
55 .of_to_plat = clk_fixed_rate_of_to_plat,
56 .plat_auto = sizeof(struct clk_fixed_rate),
57 .ops = &clk_fixed_rate_ops,
58 .flags = DM_FLAG_PRE_RELOC,
59 };
60