1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imx8mm-clock.h>
15
16 #include "clk.h"
17
18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35 static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44 };
45
46 static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48 };
49
50 static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mm_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
54 };
55
56 static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mm_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
60 };
61
62 static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mm_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
66 };
67
68 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75 static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
78 static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
79 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81 static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
84 #ifndef CONFIG_SPL_BUILD
85 static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88 static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91 static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93 #endif
94
95 static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
98 static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
99 "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
100
101 static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
102 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
103
104 static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
105 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
106
107 static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
108 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
109
110 static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
111 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
112
113 static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
114 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
115
116 static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
117 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
118
119 static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
120 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
121
122 static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
123 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
124
125 static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
126 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
127
128 static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
129 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
130
131 static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
132 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
133
imx8mm_clk_get_rate(struct clk * clk)134 static ulong imx8mm_clk_get_rate(struct clk *clk)
135 {
136 struct clk *c;
137 int ret;
138
139 debug("%s(#%lu)\n", __func__, clk->id);
140
141 ret = clk_get_by_id(clk->id, &c);
142 if (ret)
143 return ret;
144
145 return clk_get_rate(c);
146 }
147
imx8mm_clk_set_rate(struct clk * clk,unsigned long rate)148 static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
149 {
150 struct clk *c;
151 int ret;
152
153 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
154
155 ret = clk_get_by_id(clk->id, &c);
156 if (ret)
157 return ret;
158
159 return clk_set_rate(c, rate);
160 }
161
__imx8mm_clk_enable(struct clk * clk,bool enable)162 static int __imx8mm_clk_enable(struct clk *clk, bool enable)
163 {
164 struct clk *c;
165 int ret;
166
167 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
168
169 ret = clk_get_by_id(clk->id, &c);
170 if (ret)
171 return ret;
172
173 if (enable)
174 ret = clk_enable(c);
175 else
176 ret = clk_disable(c);
177
178 return ret;
179 }
180
imx8mm_clk_disable(struct clk * clk)181 static int imx8mm_clk_disable(struct clk *clk)
182 {
183 return __imx8mm_clk_enable(clk, 0);
184 }
185
imx8mm_clk_enable(struct clk * clk)186 static int imx8mm_clk_enable(struct clk *clk)
187 {
188 return __imx8mm_clk_enable(clk, 1);
189 }
190
imx8mm_clk_set_parent(struct clk * clk,struct clk * parent)191 static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
192 {
193 struct clk *c, *cp;
194 int ret;
195
196 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
197
198 ret = clk_get_by_id(clk->id, &c);
199 if (ret)
200 return ret;
201
202 ret = clk_get_by_id(parent->id, &cp);
203 if (ret)
204 return ret;
205
206 ret = clk_set_parent(c, cp);
207 c->dev->parent = cp->dev;
208
209 return ret;
210 }
211
212 static struct clk_ops imx8mm_clk_ops = {
213 .set_rate = imx8mm_clk_set_rate,
214 .get_rate = imx8mm_clk_get_rate,
215 .enable = imx8mm_clk_enable,
216 .disable = imx8mm_clk_disable,
217 .set_parent = imx8mm_clk_set_parent,
218 };
219
imx8mm_clk_probe(struct udevice * dev)220 static int imx8mm_clk_probe(struct udevice *dev)
221 {
222 void __iomem *base;
223
224 base = (void *)ANATOP_BASE_ADDR;
225
226 clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
227 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
228 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
229 clk_dm(IMX8MM_ARM_PLL_REF_SEL,
230 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
231 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
232 clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
233 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
234 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
235 clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
236 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
237 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
238 clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
239 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
240 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
241
242 clk_dm(IMX8MM_DRAM_PLL,
243 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
244 base + 0x50, &imx8mm_dram_pll));
245 clk_dm(IMX8MM_ARM_PLL,
246 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
247 base + 0x84, &imx8mm_arm_pll));
248 clk_dm(IMX8MM_SYS_PLL1,
249 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
250 base + 0x94, &imx8mm_sys_pll));
251 clk_dm(IMX8MM_SYS_PLL2,
252 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
253 base + 0x104, &imx8mm_sys_pll));
254 clk_dm(IMX8MM_SYS_PLL3,
255 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
256 base + 0x114, &imx8mm_sys_pll));
257
258 /* PLL bypass out */
259 clk_dm(IMX8MM_DRAM_PLL_BYPASS,
260 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
261 dram_pll_bypass_sels,
262 ARRAY_SIZE(dram_pll_bypass_sels),
263 CLK_SET_RATE_PARENT));
264 clk_dm(IMX8MM_ARM_PLL_BYPASS,
265 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
266 arm_pll_bypass_sels,
267 ARRAY_SIZE(arm_pll_bypass_sels),
268 CLK_SET_RATE_PARENT));
269 clk_dm(IMX8MM_SYS_PLL1_BYPASS,
270 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
271 sys_pll1_bypass_sels,
272 ARRAY_SIZE(sys_pll1_bypass_sels),
273 CLK_SET_RATE_PARENT));
274 clk_dm(IMX8MM_SYS_PLL2_BYPASS,
275 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
276 sys_pll2_bypass_sels,
277 ARRAY_SIZE(sys_pll2_bypass_sels),
278 CLK_SET_RATE_PARENT));
279 clk_dm(IMX8MM_SYS_PLL3_BYPASS,
280 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
281 sys_pll3_bypass_sels,
282 ARRAY_SIZE(sys_pll3_bypass_sels),
283 CLK_SET_RATE_PARENT));
284
285 /* PLL out gate */
286 clk_dm(IMX8MM_DRAM_PLL_OUT,
287 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
288 base + 0x50, 13));
289 clk_dm(IMX8MM_ARM_PLL_OUT,
290 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
291 base + 0x84, 11));
292 clk_dm(IMX8MM_SYS_PLL1_OUT,
293 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
294 base + 0x94, 11));
295 clk_dm(IMX8MM_SYS_PLL2_OUT,
296 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
297 base + 0x104, 11));
298 clk_dm(IMX8MM_SYS_PLL3_OUT,
299 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
300 base + 0x114, 11));
301
302 /* SYS PLL fixed output */
303 clk_dm(IMX8MM_SYS_PLL1_40M,
304 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
305 clk_dm(IMX8MM_SYS_PLL1_80M,
306 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
307 clk_dm(IMX8MM_SYS_PLL1_100M,
308 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
309 clk_dm(IMX8MM_SYS_PLL1_133M,
310 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
311 clk_dm(IMX8MM_SYS_PLL1_160M,
312 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
313 clk_dm(IMX8MM_SYS_PLL1_200M,
314 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
315 clk_dm(IMX8MM_SYS_PLL1_266M,
316 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
317 clk_dm(IMX8MM_SYS_PLL1_400M,
318 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
319 clk_dm(IMX8MM_SYS_PLL1_800M,
320 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
321
322 clk_dm(IMX8MM_SYS_PLL2_50M,
323 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
324 clk_dm(IMX8MM_SYS_PLL2_100M,
325 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
326 clk_dm(IMX8MM_SYS_PLL2_125M,
327 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
328 clk_dm(IMX8MM_SYS_PLL2_166M,
329 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
330 clk_dm(IMX8MM_SYS_PLL2_200M,
331 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
332 clk_dm(IMX8MM_SYS_PLL2_250M,
333 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
334 clk_dm(IMX8MM_SYS_PLL2_333M,
335 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
336 clk_dm(IMX8MM_SYS_PLL2_500M,
337 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
338 clk_dm(IMX8MM_SYS_PLL2_1000M,
339 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
340
341 base = dev_read_addr_ptr(dev);
342 if (!base)
343 return -EINVAL;
344
345 clk_dm(IMX8MM_CLK_A53_SRC,
346 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
347 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
348 clk_dm(IMX8MM_CLK_A53_CG,
349 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
350 clk_dm(IMX8MM_CLK_A53_DIV,
351 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
352 base + 0x8000, 0, 3));
353
354 clk_dm(IMX8MM_CLK_AHB,
355 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
356 base + 0x9000));
357 clk_dm(IMX8MM_CLK_IPG_ROOT,
358 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
359
360 clk_dm(IMX8MM_CLK_ENET_AXI,
361 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
362 base + 0x8880));
363 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
364 imx8m_clk_composite_critical("nand_usdhc_bus",
365 imx8mm_nand_usdhc_sels,
366 base + 0x8900));
367 clk_dm(IMX8MM_CLK_USB_BUS,
368 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
369
370 /* IP */
371 clk_dm(IMX8MM_CLK_USDHC1,
372 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
373 base + 0xac00));
374 clk_dm(IMX8MM_CLK_USDHC2,
375 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
376 base + 0xac80));
377 clk_dm(IMX8MM_CLK_I2C1,
378 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
379 clk_dm(IMX8MM_CLK_I2C2,
380 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
381 clk_dm(IMX8MM_CLK_I2C3,
382 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
383 clk_dm(IMX8MM_CLK_I2C4,
384 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
385 clk_dm(IMX8MM_CLK_WDOG,
386 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
387 clk_dm(IMX8MM_CLK_USDHC3,
388 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
389 base + 0xbc80));
390 clk_dm(IMX8MM_CLK_QSPI,
391 imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
392 clk_dm(IMX8MM_CLK_USB_CORE_REF,
393 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
394 clk_dm(IMX8MM_CLK_USB_PHY_REF,
395 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
396
397 clk_dm(IMX8MM_CLK_I2C1_ROOT,
398 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
399 clk_dm(IMX8MM_CLK_I2C2_ROOT,
400 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
401 clk_dm(IMX8MM_CLK_I2C3_ROOT,
402 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
403 clk_dm(IMX8MM_CLK_I2C4_ROOT,
404 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
405 clk_dm(IMX8MM_CLK_OCOTP_ROOT,
406 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
407 clk_dm(IMX8MM_CLK_USDHC1_ROOT,
408 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
409 clk_dm(IMX8MM_CLK_USDHC2_ROOT,
410 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
411 clk_dm(IMX8MM_CLK_WDOG1_ROOT,
412 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
413 clk_dm(IMX8MM_CLK_WDOG2_ROOT,
414 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
415 clk_dm(IMX8MM_CLK_WDOG3_ROOT,
416 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
417 clk_dm(IMX8MM_CLK_USDHC3_ROOT,
418 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
419 clk_dm(IMX8MM_CLK_QSPI_ROOT,
420 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
421 clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
422 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
423
424 /* clks not needed in SPL stage */
425 #ifndef CONFIG_SPL_BUILD
426 clk_dm(IMX8MM_CLK_ENET_REF,
427 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
428 base + 0xa980));
429 clk_dm(IMX8MM_CLK_ENET_TIMER,
430 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
431 base + 0xaa00));
432 clk_dm(IMX8MM_CLK_ENET_PHY_REF,
433 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
434 base + 0xaa80));
435 clk_dm(IMX8MM_CLK_ENET1_ROOT,
436 imx_clk_gate4("enet1_root_clk", "enet_axi",
437 base + 0x40a0, 0));
438 #endif
439
440 return 0;
441 }
442
443 static const struct udevice_id imx8mm_clk_ids[] = {
444 { .compatible = "fsl,imx8mm-ccm" },
445 { },
446 };
447
448 U_BOOT_DRIVER(imx8mm_clk) = {
449 .name = "clk_imx8mm",
450 .id = UCLASS_CLK,
451 .of_match = imx8mm_clk_ids,
452 .ops = &imx8mm_clk_ops,
453 .probe = imx8mm_clk_probe,
454 .flags = DM_FLAG_PRE_RELOC,
455 };
456