1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imx8mp-clock.h>
15
16 #include "clk.h"
17
18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35 static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44 };
45
46 static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48 };
49
50 static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mp_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
54 };
55
56 static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mp_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
60 };
61
62 static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mp_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
66 };
67
68 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75 static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
76 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
77 "audio_pll1_out", "sys_pll3_out", };
78
79 static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
80 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
81 "video_pll1_out", "sys_pll1_100m",};
82
83 static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
84 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
85 "video_pll1_out", "sys_pll3_out", };
86
87 static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
88 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
89 "sys_pll2_250m", "audio_pll1_out", };
90
91 static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
92 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
93 "video_pll1_out", "audio_pll2_out", };
94
95 static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
96 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
97 "video_pll1_out", "audio_pll2_out", };
98
99 static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
100 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
101 "audio_pll1_out", "video_pll1_out", };
102
103 static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
104 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
105 "audio_pll1_out", "sys_pll1_266m", };
106
107 static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
108 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
109 "sys_pll2_250m", "audio_pll2_out", };
110
111 static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
112 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
113 "audio_pll2_out", "sys_pll1_133m", };
114
115 static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
116 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
117 "audio_pll2_out", "sys_pll1_133m", };
118
119 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
120 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
121 "audio_pll2_out", "sys_pll1_100m", };
122
123 static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
124 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
125 "audio_pll2_out", "sys_pll1_100m", };
126
127 static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
128 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
129 "audio_pll2_out", "sys_pll1_133m", };
130
131 static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
132 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
133 "audio_pll2_out", "sys_pll1_133m", };
134
135 static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
136 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
137 "audio_pll2_out", "sys_pll1_133m", };
138
139 static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
140 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
141 "audio_pll2_out", "sys_pll1_133m", };
142
143 static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
144 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
145 "clk_ext4", "audio_pll2_out", };
146
147 static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
148 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
149 "clk_ext3", "audio_pll2_out", };
150
151 static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
152 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
153 "clk_ext4", "audio_pll2_out", };
154
155 static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
156 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
157 "clk_ext3", "audio_pll2_out", };
158
159 static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
160 "sys_pll2_100m", "sys_pll1_800m",
161 "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
162
163 static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
164 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
165 "sys_pll1_80m", "sys_pll2_166m" };
166
167 static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
168 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
169 "sys_pll3_out", "sys_pll1_100m", };
170
171 static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
172 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
173 "audio_pll2_out", "sys_pll1_100m", };
174
175 static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
176 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
177 "video_pll1_out", "clk_ext4", };
178
179 static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
180 "clk_ext1", "clk_ext2", "clk_ext3",
181 "clk_ext4", "video_pll1_out", };
182
183 static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
184 "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
185 "video_pll1_out", "audio_pll2_out", };
186
187 static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
188
189
imx8mp_clk_get_rate(struct clk * clk)190 static ulong imx8mp_clk_get_rate(struct clk *clk)
191 {
192 struct clk *c;
193 int ret;
194
195 debug("%s(#%lu)\n", __func__, clk->id);
196
197 ret = clk_get_by_id(clk->id, &c);
198 if (ret)
199 return ret;
200
201 return clk_get_rate(c);
202 }
203
imx8mp_clk_set_rate(struct clk * clk,unsigned long rate)204 static ulong imx8mp_clk_set_rate(struct clk *clk, unsigned long rate)
205 {
206 struct clk *c;
207 int ret;
208
209 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
210
211 ret = clk_get_by_id(clk->id, &c);
212 if (ret)
213 return ret;
214
215 return clk_set_rate(c, rate);
216 }
217
__imx8mp_clk_enable(struct clk * clk,bool enable)218 static int __imx8mp_clk_enable(struct clk *clk, bool enable)
219 {
220 struct clk *c;
221 int ret;
222
223 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
224
225 ret = clk_get_by_id(clk->id, &c);
226 if (ret)
227 return ret;
228
229 if (enable)
230 ret = clk_enable(c);
231 else
232 ret = clk_disable(c);
233
234 return ret;
235 }
236
imx8mp_clk_disable(struct clk * clk)237 static int imx8mp_clk_disable(struct clk *clk)
238 {
239 return __imx8mp_clk_enable(clk, 0);
240 }
241
imx8mp_clk_enable(struct clk * clk)242 static int imx8mp_clk_enable(struct clk *clk)
243 {
244 return __imx8mp_clk_enable(clk, 1);
245 }
246
imx8mp_clk_set_parent(struct clk * clk,struct clk * parent)247 static int imx8mp_clk_set_parent(struct clk *clk, struct clk *parent)
248 {
249 struct clk *c, *cp;
250 int ret;
251
252 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
253
254 ret = clk_get_by_id(clk->id, &c);
255 if (ret)
256 return ret;
257
258 ret = clk_get_by_id(parent->id, &cp);
259 if (ret)
260 return ret;
261
262 ret = clk_set_parent(c, cp);
263
264 c->dev->parent = cp->dev;
265
266 return ret;
267 }
268
269 static struct clk_ops imx8mp_clk_ops = {
270 .set_rate = imx8mp_clk_set_rate,
271 .get_rate = imx8mp_clk_get_rate,
272 .enable = imx8mp_clk_enable,
273 .disable = imx8mp_clk_disable,
274 .set_parent = imx8mp_clk_set_parent,
275 };
276
imx8mp_clk_probe(struct udevice * dev)277 static int imx8mp_clk_probe(struct udevice *dev)
278 {
279 void __iomem *base;
280
281 base = (void *)ANATOP_BASE_ADDR;
282
283 clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
284 clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
285 clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
286 clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
287 clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
288
289 clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
290 clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
291 clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
292 clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
293 clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
294
295 clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
296 clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
297 clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
298 clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
299 clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
300
301 clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
302 clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
303 clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
304 clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
305 clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
306
307 clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
308 clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
309 clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
310 clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
311 clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
312 clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
313 clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
314 clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
315 clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
316
317 clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
318 clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
319 clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
320 clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
321 clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
322 clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
323 clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
324 clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
325 clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
326
327 base = dev_read_addr_ptr(dev);
328 if (!base)
329 return -EINVAL;
330
331 clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
332 clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
333 clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
334
335 clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
336 clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
337 clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
338 clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
339 clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
340
341 clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
342
343 clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
344
345 clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
346 clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
347 clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
348 clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
349 clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
350 clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
351 clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
352 clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
353 clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
354 clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
355 clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
356 clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
357 clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
358 clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
359
360 clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
361 clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
362 clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
363 clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
364 clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
365
366 clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
367 clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
368
369 clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
370 clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
371
372 clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
373
374 clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
375 clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
376 clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
377 clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
378 clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
379 clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
380 clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
381 clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
382 clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
383 clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
384 clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
385 clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
386 clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
387 clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
388 clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
389 clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
390 clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
391 clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
392 clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
393 clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
394 clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
395 clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
396 clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
397
398 clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
399
400 return 0;
401 }
402
403 static const struct udevice_id imx8mp_clk_ids[] = {
404 { .compatible = "fsl,imx8mp-ccm" },
405 { },
406 };
407
408 U_BOOT_DRIVER(imx8mp_clk) = {
409 .name = "clk_imx8mp",
410 .id = UCLASS_CLK,
411 .of_match = imx8mp_clk_ids,
412 .ops = &imx8mp_clk_ops,
413 .probe = imx8mp_clk_probe,
414 .flags = DM_FLAG_PRE_RELOC,
415 };
416