1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun50i-a64-ccu.h>
13 #include <dt-bindings/reset/sun50i-a64-ccu.h>
14 #include <linux/bitops.h>
15
16 static const struct ccu_clk_gate a64_gates[] = {
17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
27 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
28
29 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
30 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
31 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
32 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
33 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
34
35 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
36 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
37
38 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
39 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
40 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
41 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
42 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
43 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
44 };
45
46 static const struct ccu_reset a64_resets[] = {
47 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
48 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
49 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
50
51 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
52 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
53 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
54 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
55 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
56 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
57 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
58 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
59 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
60 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
61 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
62
63 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
64 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
65 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
66 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
67 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
68 };
69
70 static const struct ccu_desc a64_ccu_desc = {
71 .gates = a64_gates,
72 .resets = a64_resets,
73 };
74
a64_clk_bind(struct udevice * dev)75 static int a64_clk_bind(struct udevice *dev)
76 {
77 return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
78 }
79
80 static const struct udevice_id a64_ccu_ids[] = {
81 { .compatible = "allwinner,sun50i-a64-ccu",
82 .data = (ulong)&a64_ccu_desc },
83 { }
84 };
85
86 U_BOOT_DRIVER(clk_sun50i_a64) = {
87 .name = "sun50i_a64_ccu",
88 .id = UCLASS_CLK,
89 .of_match = a64_ccu_ids,
90 .priv_auto = sizeof(struct ccu_priv),
91 .ops = &sunxi_clk_ops,
92 .probe = sunxi_clk_probe,
93 .bind = a64_clk_bind,
94 };
95