1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: http://processors.wiki.ti.com/index.php/TISCI for details 8 * 9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 10 * Based on drivers/firmware/ti_sci.h from Linux. 11 * 12 */ 13 14 #ifndef __TI_SCI_H 15 #define __TI_SCI_H 16 17 /* Generic Messages */ 18 #include <linux/bitops.h> 19 #define TI_SCI_MSG_ENABLE_WDT 0x0000 20 #define TI_SCI_MSG_WAKE_RESET 0x0001 21 #define TI_SCI_MSG_VERSION 0x0002 22 #define TI_SCI_MSG_WAKE_REASON 0x0003 23 #define TI_SCI_MSG_GOODBYE 0x0004 24 #define TI_SCI_MSG_SYS_RESET 0x0005 25 #define TI_SCI_MSG_BOARD_CONFIG 0x000b 26 #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c 27 #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d 28 #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e 29 #define TISCI_MSG_QUERY_MSMC 0x0020 30 31 /* Device requests */ 32 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 33 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 34 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 35 36 /* Clock requests */ 37 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 38 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 39 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 40 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 41 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 42 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 43 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 44 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 45 46 /* Processor Control Messages */ 47 #define TISCI_MSG_PROC_REQUEST 0xc000 48 #define TISCI_MSG_PROC_RELEASE 0xc001 49 #define TISCI_MSG_PROC_HANDOVER 0xc005 50 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100 51 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101 52 #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120 53 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400 54 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401 55 56 /* Resource Management Requests */ 57 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 58 59 /* NAVSS resource management */ 60 /* Ringacc requests */ 61 #define TI_SCI_MSG_RM_RING_CFG 0x1110 62 63 /* PSI-L requests */ 64 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 65 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 66 67 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 68 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 69 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 70 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 71 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 72 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 73 74 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 75 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 76 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 77 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 78 79 #define TISCI_MSG_FWL_SET 0x9000 80 #define TISCI_MSG_FWL_GET 0x9001 81 #define TISCI_MSG_FWL_CHANGE_OWNER 0x9002 82 83 /** 84 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 85 * @type: Type of messages: One of TI_SCI_MSG* values 86 * @host: Host of the message 87 * @seq: Message identifier indicating a transfer sequence 88 * @flags: Flag for the message 89 */ 90 struct ti_sci_msg_hdr { 91 u16 type; 92 u8 host; 93 u8 seq; 94 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 95 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 96 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 97 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 98 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 99 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 100 /* Additional Flags */ 101 u32 flags; 102 } __packed; 103 104 /** 105 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent 106 * via secure transport. 107 * @checksum: crc16 checksum for the entire message 108 * @reserved: Reserved for future use. 109 */ 110 struct ti_sci_secure_msg_hdr { 111 u16 checksum; 112 u16 reserved; 113 } __packed; 114 115 /** 116 * struct ti_sci_msg_resp_version - Response for a message 117 * @hdr: Generic header 118 * @firmware_description: String describing the firmware 119 * @firmware_revision: Firmware revision 120 * @abi_major: Major version of the ABI that firmware supports 121 * @abi_minor: Minor version of the ABI that firmware supports 122 * 123 * In general, ABI version changes follow the rule that minor version increments 124 * are backward compatible. Major revision changes in ABI may not be 125 * backward compatible. 126 * 127 * Response to a generic message with message type TI_SCI_MSG_VERSION 128 */ 129 struct ti_sci_msg_resp_version { 130 struct ti_sci_msg_hdr hdr; 131 char firmware_description[32]; 132 u16 firmware_revision; 133 u8 abi_major; 134 u8 abi_minor; 135 } __packed; 136 137 /** 138 * struct ti_sci_msg_req_reboot - Reboot the SoC 139 * @hdr: Generic Header 140 * 141 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 142 * ACK/NACK message. 143 */ 144 struct ti_sci_msg_req_reboot { 145 struct ti_sci_msg_hdr hdr; 146 } __packed; 147 148 /** 149 * struct ti_sci_msg_board_config - Board configuration message 150 * @hdr: Generic Header 151 * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board 152 * configuration data 153 * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board 154 * configuration data 155 * @boardcfg_size: Size of board configuration data object 156 * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic 157 * ACK/NACK message. 158 */ 159 struct ti_sci_msg_board_config { 160 struct ti_sci_msg_hdr hdr; 161 u32 boardcfgp_low; 162 u32 boardcfgp_high; 163 u16 boardcfg_size; 164 } __packed; 165 166 /** 167 * struct ti_sci_msg_resp_query_msmc - Query msmc message response structure 168 * @hdr: Generic Header 169 * @msmc_start_low: Lower 32 bit of msmc start 170 * @msmc_start_high: Upper 32 bit of msmc start 171 * @msmc_end_low: Lower 32 bit of msmc end 172 * @msmc_end_high: Upper 32 bit of msmc end 173 * 174 * Response to a generic message with message type TISCI_MSG_QUERY_MSMC 175 */ 176 struct ti_sci_msg_resp_query_msmc { 177 struct ti_sci_msg_hdr hdr; 178 u32 msmc_start_low; 179 u32 msmc_start_high; 180 u32 msmc_end_low; 181 u32 msmc_end_high; 182 } __packed; 183 184 /** 185 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 186 * @hdr: Generic header 187 * @id: Indicates which device to modify 188 * @reserved: Reserved space in message, must be 0 for backward compatibility 189 * @state: The desired state of the device. 190 * 191 * Certain flags can also be set to alter the device state: 192 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 193 * The meaning of this flag will vary slightly from device to device and from 194 * SoC to SoC but it generally allows the device to wake the SoC out of deep 195 * suspend states. 196 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 197 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 198 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 199 * If another host already has this device set to STATE_RETENTION or STATE_ON, 200 * the message will fail. Once successful, other hosts attempting to set 201 * STATE_RETENTION or STATE_ON will fail. 202 * 203 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 204 * ACK/NACK message. 205 */ 206 struct ti_sci_msg_req_set_device_state { 207 /* Additional hdr->flags options */ 208 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 209 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 210 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 211 struct ti_sci_msg_hdr hdr; 212 u32 id; 213 u32 reserved; 214 215 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 216 #define MSG_DEVICE_SW_STATE_RETENTION 1 217 #define MSG_DEVICE_SW_STATE_ON 2 218 u8 state; 219 } __packed; 220 221 /** 222 * struct ti_sci_msg_req_get_device_state - Request to get device. 223 * @hdr: Generic header 224 * @id: Device Identifier 225 * 226 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 227 * information 228 */ 229 struct ti_sci_msg_req_get_device_state { 230 struct ti_sci_msg_hdr hdr; 231 u32 id; 232 } __packed; 233 234 /** 235 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 236 * @hdr: Generic header 237 * @context_loss_count: Indicates how many times the device has lost context. A 238 * driver can use this monotonic counter to determine if the device has 239 * lost context since the last time this message was exchanged. 240 * @resets: Programmed state of the reset lines. 241 * @programmed_state: The state as programmed by set_device. 242 * - Uses the MSG_DEVICE_SW_* macros 243 * @current_state: The actual state of the hardware. 244 * 245 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 246 */ 247 struct ti_sci_msg_resp_get_device_state { 248 struct ti_sci_msg_hdr hdr; 249 u32 context_loss_count; 250 u32 resets; 251 u8 programmed_state; 252 #define MSG_DEVICE_HW_STATE_OFF 0 253 #define MSG_DEVICE_HW_STATE_ON 1 254 #define MSG_DEVICE_HW_STATE_TRANS 2 255 u8 current_state; 256 } __packed; 257 258 /** 259 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 260 * configuration of the device 261 * @hdr: Generic header 262 * @id: Indicates which device to modify 263 * @resets: A bit field of resets for the device. The meaning, behavior, 264 * and usage of the reset flags are device specific. 0 for a bit 265 * indicates releasing the reset represented by that bit while 1 266 * indicates keeping it held. 267 * 268 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 269 * ACK/NACK message. 270 */ 271 struct ti_sci_msg_req_set_device_resets { 272 struct ti_sci_msg_hdr hdr; 273 u32 id; 274 u32 resets; 275 } __packed; 276 277 /** 278 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 279 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 280 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 281 * via spread spectrum clocking. 282 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 283 * frequency to be changed while it is running so long as it 284 * is within the min/max limits. 285 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 286 * is only applicable to clock inputs on the SoC pseudo-device. 287 * @dev_id: Device identifier this request is for 288 * @clk_id: Clock identifier for the device for this request. 289 * Each device has it's own set of clock inputs. This indexes 290 * which clock input to modify. 291 * @request_state: Request the state for the clock to be set to. 292 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 293 * it can be disabled, regardless of the state of the device 294 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 295 * automatically manage the state of this clock. If the device 296 * is enabled, then the clock is enabled. If the device is set 297 * to off or retention, then the clock is internally set as not 298 * being required by the device.(default) 299 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 300 * regardless of the state of the device. 301 * 302 * Normally, all required clocks are managed by TISCI entity, this is used 303 * only for specific control *IF* required. Auto managed state is 304 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 305 * will explicitly control. 306 * 307 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 308 * ACK or NACK message. 309 */ 310 struct ti_sci_msg_req_set_clock_state { 311 /* Additional hdr->flags options */ 312 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 313 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 314 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 315 struct ti_sci_msg_hdr hdr; 316 u32 dev_id; 317 u8 clk_id; 318 #define MSG_CLOCK_SW_STATE_UNREQ 0 319 #define MSG_CLOCK_SW_STATE_AUTO 1 320 #define MSG_CLOCK_SW_STATE_REQ 2 321 u8 request_state; 322 } __packed; 323 324 /** 325 * struct ti_sci_msg_req_get_clock_state - Request for clock state 326 * @hdr: Generic Header 327 * @dev_id: Device identifier this request is for 328 * @clk_id: Clock identifier for the device for this request. 329 * Each device has it's own set of clock inputs. This indexes 330 * which clock input to get state of. 331 * 332 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 333 * of the clock 334 */ 335 struct ti_sci_msg_req_get_clock_state { 336 struct ti_sci_msg_hdr hdr; 337 u32 dev_id; 338 u8 clk_id; 339 } __packed; 340 341 /** 342 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 343 * @hdr: Generic Header 344 * @programmed_state: Any programmed state of the clock. This is one of 345 * MSG_CLOCK_SW_STATE* values. 346 * @current_state: Current state of the clock. This is one of: 347 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 348 * MSG_CLOCK_HW_STATE_READY: Clock is ready 349 * 350 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 351 */ 352 struct ti_sci_msg_resp_get_clock_state { 353 struct ti_sci_msg_hdr hdr; 354 u8 programmed_state; 355 #define MSG_CLOCK_HW_STATE_NOT_READY 0 356 #define MSG_CLOCK_HW_STATE_READY 1 357 u8 current_state; 358 } __packed; 359 360 /** 361 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 362 * @hdr: Generic Header 363 * @dev_id: Device identifier this request is for 364 * @clk_id: Clock identifier for the device for this request. 365 * Each device has it's own set of clock inputs. This indexes 366 * which clock input to modify. 367 * @parent_id: The new clock parent is selectable by an index via this 368 * parameter. 369 * 370 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 371 * ACK / NACK message. 372 */ 373 struct ti_sci_msg_req_set_clock_parent { 374 struct ti_sci_msg_hdr hdr; 375 u32 dev_id; 376 u8 clk_id; 377 u8 parent_id; 378 } __packed; 379 380 /** 381 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 382 * @hdr: Generic Header 383 * @dev_id: Device identifier this request is for 384 * @clk_id: Clock identifier for the device for this request. 385 * Each device has it's own set of clock inputs. This indexes 386 * which clock input to get the parent for. 387 * 388 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 389 */ 390 struct ti_sci_msg_req_get_clock_parent { 391 struct ti_sci_msg_hdr hdr; 392 u32 dev_id; 393 u8 clk_id; 394 } __packed; 395 396 /** 397 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 398 * @hdr: Generic Header 399 * @parent_id: The current clock parent 400 * 401 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 402 */ 403 struct ti_sci_msg_resp_get_clock_parent { 404 struct ti_sci_msg_hdr hdr; 405 u8 parent_id; 406 } __packed; 407 408 /** 409 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 410 * @hdr: Generic header 411 * @dev_id: Device identifier this request is for 412 * @clk_id: Clock identifier for the device for this request. 413 * 414 * This request provides information about how many clock parent options 415 * are available for a given clock to a device. This is typically used 416 * for input clocks. 417 * 418 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 419 * message, or NACK in case of inability to satisfy request. 420 */ 421 struct ti_sci_msg_req_get_clock_num_parents { 422 struct ti_sci_msg_hdr hdr; 423 u32 dev_id; 424 u8 clk_id; 425 } __packed; 426 427 /** 428 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 429 * @hdr: Generic header 430 * @num_parents: Number of clock parents 431 * 432 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 433 */ 434 struct ti_sci_msg_resp_get_clock_num_parents { 435 struct ti_sci_msg_hdr hdr; 436 u8 num_parents; 437 } __packed; 438 439 /** 440 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 441 * @hdr: Generic Header 442 * @dev_id: Device identifier this request is for 443 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 444 * allowable programmed frequency and does not account for clock 445 * tolerances and jitter. 446 * @target_freq_hz: The target clock frequency. A frequency will be found 447 * as close to this target frequency as possible. 448 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 449 * allowable programmed frequency and does not account for clock 450 * tolerances and jitter. 451 * @clk_id: Clock identifier for the device for this request. 452 * 453 * NOTE: Normally clock frequency management is automatically done by TISCI 454 * entity. In case of specific requests, TISCI evaluates capability to achieve 455 * requested frequency within provided range and responds with 456 * result message. 457 * 458 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 459 * or NACK in case of inability to satisfy request. 460 */ 461 struct ti_sci_msg_req_query_clock_freq { 462 struct ti_sci_msg_hdr hdr; 463 u32 dev_id; 464 u64 min_freq_hz; 465 u64 target_freq_hz; 466 u64 max_freq_hz; 467 u8 clk_id; 468 } __packed; 469 470 /** 471 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 472 * @hdr: Generic Header 473 * @freq_hz: Frequency that is the best match in Hz. 474 * 475 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 476 * cannot be satisfied, the message will be of type NACK. 477 */ 478 struct ti_sci_msg_resp_query_clock_freq { 479 struct ti_sci_msg_hdr hdr; 480 u64 freq_hz; 481 } __packed; 482 483 /** 484 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 485 * @hdr: Generic Header 486 * @dev_id: Device identifier this request is for 487 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 488 * allowable programmed frequency and does not account for clock 489 * tolerances and jitter. 490 * @target_freq_hz: The target clock frequency. The clock will be programmed 491 * at a rate as close to this target frequency as possible. 492 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 493 * allowable programmed frequency and does not account for clock 494 * tolerances and jitter. 495 * @clk_id: Clock identifier for the device for this request. 496 * 497 * NOTE: Normally clock frequency management is automatically done by TISCI 498 * entity. In case of specific requests, TISCI evaluates capability to achieve 499 * requested range and responds with success/failure message. 500 * 501 * This sets the desired frequency for a clock within an allowable 502 * range. This message will fail on an enabled clock unless 503 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 504 * if other clocks have their frequency modified due to this message, 505 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 506 * 507 * Calling set frequency on a clock input to the SoC pseudo-device will 508 * inform the PMMC of that clock's frequency. Setting a frequency of 509 * zero will indicate the clock is disabled. 510 * 511 * Calling set frequency on clock outputs from the SoC pseudo-device will 512 * function similarly to setting the clock frequency on a device. 513 * 514 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 515 * message. 516 */ 517 struct ti_sci_msg_req_set_clock_freq { 518 struct ti_sci_msg_hdr hdr; 519 u32 dev_id; 520 u64 min_freq_hz; 521 u64 target_freq_hz; 522 u64 max_freq_hz; 523 u8 clk_id; 524 } __packed; 525 526 /** 527 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 528 * @hdr: Generic Header 529 * @dev_id: Device identifier this request is for 530 * @clk_id: Clock identifier for the device for this request. 531 * 532 * NOTE: Normally clock frequency management is automatically done by TISCI 533 * entity. In some cases, clock frequencies are configured by host. 534 * 535 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 536 * that the clock is currently at. 537 */ 538 struct ti_sci_msg_req_get_clock_freq { 539 struct ti_sci_msg_hdr hdr; 540 u32 dev_id; 541 u8 clk_id; 542 } __packed; 543 544 /** 545 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 546 * @hdr: Generic Header 547 * @freq_hz: Frequency that the clock is currently on, in Hz. 548 * 549 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 550 */ 551 struct ti_sci_msg_resp_get_clock_freq { 552 struct ti_sci_msg_hdr hdr; 553 u64 freq_hz; 554 } __packed; 555 556 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 557 558 /** 559 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 560 * range of resources. 561 * @hdr: Generic Header 562 * @type: Unique resource assignment type 563 * @subtype: Resource assignment subtype within the resource type. 564 * @secondary_host: Host processing entity to which the resources are 565 * allocated. This is required only when the destination 566 * host id id different from ti sci interface host id, 567 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 568 * 569 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 570 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 571 */ 572 struct ti_sci_msg_req_get_resource_range { 573 struct ti_sci_msg_hdr hdr; 574 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 575 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 576 u16 type; 577 u8 subtype; 578 u8 secondary_host; 579 } __packed; 580 581 /** 582 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 583 * @hdr: Generic Header 584 * @range_start: Start index of the resource range. 585 * @range_num: Number of resources in the range. 586 * 587 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 588 */ 589 struct ti_sci_msg_resp_get_resource_range { 590 struct ti_sci_msg_hdr hdr; 591 u16 range_start; 592 u16 range_num; 593 } __packed; 594 595 #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 596 #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 597 #define TISCI_ADDR_HIGH_SHIFT 32 598 599 /** 600 * struct ti_sci_msg_req_proc_request - Request a processor 601 * 602 * @hdr: Generic Header 603 * @processor_id: ID of processor 604 * 605 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 606 * message. 607 */ 608 struct ti_sci_msg_req_proc_request { 609 struct ti_sci_msg_hdr hdr; 610 u8 processor_id; 611 } __packed; 612 613 /** 614 * struct ti_sci_msg_req_proc_release - Release a processor 615 * 616 * @hdr: Generic Header 617 * @processor_id: ID of processor 618 * 619 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 620 * message. 621 */ 622 struct ti_sci_msg_req_proc_release { 623 struct ti_sci_msg_hdr hdr; 624 u8 processor_id; 625 } __packed; 626 627 /** 628 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 629 * 630 * @hdr: Generic Header 631 * @processor_id: ID of processor 632 * @host_id: New Host we want to give control to 633 * 634 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 635 * message. 636 */ 637 struct ti_sci_msg_req_proc_handover { 638 struct ti_sci_msg_hdr hdr; 639 u8 processor_id; 640 u8 host_id; 641 } __packed; 642 643 /* A53 Config Flags */ 644 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001 645 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002 646 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004 647 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008 648 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100 649 650 /* R5 Config Flags */ 651 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001 652 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002 653 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 654 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200 655 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400 656 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800 657 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 658 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 659 660 /** 661 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration 662 * @hdr: Generic Header 663 * @processor_id: ID of processor 664 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 665 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 666 * @config_flags_set: Optional Processor specific Config Flags to set. 667 * Setting a bit here implies required bit sets to 1. 668 * @config_flags_clear: Optional Processor specific Config Flags to clear. 669 * Setting a bit here implies required bit gets cleared. 670 * 671 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic 672 * ACK/NACK message. 673 */ 674 struct ti_sci_msg_req_set_proc_boot_config { 675 struct ti_sci_msg_hdr hdr; 676 u8 processor_id; 677 u32 bootvector_low; 678 u32 bootvector_high; 679 u32 config_flags_set; 680 u32 config_flags_clear; 681 } __packed; 682 683 /* R5 Control Flags */ 684 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 685 686 /** 687 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags 688 * @hdr: Generic Header 689 * @processor_id: ID of processor 690 * @control_flags_set: Optional Processor specific Control Flags to set. 691 * Setting a bit here implies required bit sets to 1. 692 * @control_flags_clear:Optional Processor specific Control Flags to clear. 693 * Setting a bit here implies required bit gets cleared. 694 * 695 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK 696 * message. 697 */ 698 struct ti_sci_msg_req_set_proc_boot_ctrl { 699 struct ti_sci_msg_hdr hdr; 700 u8 processor_id; 701 u32 control_flags_set; 702 u32 control_flags_clear; 703 } __packed; 704 705 /** 706 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image 707 * @hdr: Generic Header 708 * @cert_addr_low: Lower 32bit (Little Endian) of certificate 709 * @cert_addr_high: Higher 32bit (Little Endian) of certificate 710 * 711 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic 712 * ACK/NACK message. 713 */ 714 struct ti_sci_msg_req_proc_auth_boot_image { 715 struct ti_sci_msg_hdr hdr; 716 u32 cert_addr_low; 717 u32 cert_addr_high; 718 } __packed; 719 720 struct ti_sci_msg_resp_proc_auth_boot_image { 721 struct ti_sci_msg_hdr hdr; 722 u32 image_addr_low; 723 u32 image_addr_high; 724 u32 image_size; 725 } __packed; 726 727 /** 728 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status 729 * @hdr: Generic Header 730 * @processor_id: ID of processor 731 * 732 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate 733 * message, or NACK in case of inability to satisfy request. 734 */ 735 struct ti_sci_msg_req_get_proc_boot_status { 736 struct ti_sci_msg_hdr hdr; 737 u8 processor_id; 738 } __packed; 739 740 /* ARMv8 Status Flags */ 741 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001 742 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002 743 744 /* R5 Status Flags */ 745 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 746 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 747 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004 748 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100 749 750 /** 751 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response 752 * @hdr: Generic Header 753 * @processor_id: ID of processor 754 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 755 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 756 * @config_flags: Optional Processor specific Config Flags set. 757 * @control_flags: Optional Processor specific Control Flags. 758 * @status_flags: Optional Processor specific Status Flags set. 759 * 760 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS. 761 */ 762 struct ti_sci_msg_resp_get_proc_boot_status { 763 struct ti_sci_msg_hdr hdr; 764 u8 processor_id; 765 u32 bootvector_low; 766 u32 bootvector_high; 767 u32 config_flags; 768 u32 control_flags; 769 u32 status_flags; 770 } __packed; 771 772 /** 773 * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor 774 * boot status 775 * @hdr: Generic Header 776 * @processor_id: ID of processor 777 * @num_wait_iterations: Total number of iterations we will check before 778 * we will timeout and give up 779 * @num_match_iterations: How many iterations should we have continued 780 * status to account for status bits glitching. 781 * This is to make sure that match occurs for 782 * consecutive checks. This implies that the 783 * worst case should consider that the stable 784 * time should at the worst be num_wait_iterations 785 * num_match_iterations to prevent timeout. 786 * @delay_per_iteration_us: Specifies how long to wait (in micro seconds) 787 * between each status checks. This is the minimum 788 * duration, and overhead of register reads and 789 * checks are on top of this and can vary based on 790 * varied conditions. 791 * @delay_before_iterations_us: Specifies how long to wait (in micro seconds) 792 * before the very first check in the first 793 * iteration of status check loop. This is the 794 * minimum duration, and overhead of register 795 * reads and checks are. 796 * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the 797 * status matching this field requested MUST be 1. 798 * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the 799 * bits matching this field requested MUST be 1. 800 * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the 801 * status matching this field requested MUST be 0. 802 * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the 803 * bits matching this field requested MUST be 0. 804 * 805 * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate 806 * message, or NACK in case of inability to satisfy request. 807 */ 808 struct ti_sci_msg_req_wait_proc_boot_status { 809 struct ti_sci_msg_hdr hdr; 810 u8 processor_id; 811 u8 num_wait_iterations; 812 u8 num_match_iterations; 813 u8 delay_per_iteration_us; 814 u8 delay_before_iterations_us; 815 u32 status_flags_1_set_all_wait; 816 u32 status_flags_1_set_any_wait; 817 u32 status_flags_1_clr_all_wait; 818 u32 status_flags_1_clr_any_wait; 819 } __packed; 820 821 /** 822 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 823 * 824 * Configures the non-real-time registers of a Navigator Subsystem ring. 825 * @hdr: Generic Header 826 * @valid_params: Bitfield defining validity of ring configuration parameters. 827 * The ring configuration fields are not valid, and will not be used for 828 * ring configuration, if their corresponding valid bit is zero. 829 * Valid bit usage: 830 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 831 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 832 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 833 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 834 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 835 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 836 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 837 * @index: ring index to be configured. 838 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 839 * RING_BA_LO register 840 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 841 * RING_BA_HI register. 842 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 843 * modes. 844 * @mode: Specifies the mode the ring is to be configured. 845 * @size: Specifies encoded ring element size. To calculate the encoded size use 846 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 847 * greater than 256. 848 * @order_id: Specifies the ring's bus order ID. 849 */ 850 struct ti_sci_msg_rm_ring_cfg_req { 851 struct ti_sci_msg_hdr hdr; 852 u32 valid_params; 853 u16 nav_id; 854 u16 index; 855 u32 addr_lo; 856 u32 addr_hi; 857 u32 count; 858 u8 mode; 859 u8 size; 860 u8 order_id; 861 } __packed; 862 863 /** 864 * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring. 865 * 866 * @hdr: Generic Header 867 */ 868 struct ti_sci_msg_rm_ring_cfg_resp { 869 struct ti_sci_msg_hdr hdr; 870 } __packed; 871 872 /** 873 * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration 874 * 875 * Gets the configuration of the non-real-time register fields of a ring. The 876 * host, or a supervisor of the host, who owns the ring must be the requesting 877 * host. The values of the non-real-time registers are returned in 878 * @ti_sci_msg_rm_ring_get_cfg_resp. 879 * 880 * @hdr: Generic Header 881 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 882 * @index: ring index. 883 */ 884 struct ti_sci_msg_rm_ring_get_cfg_req { 885 struct ti_sci_msg_hdr hdr; 886 u16 nav_id; 887 u16 index; 888 } __packed; 889 890 /** 891 * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response 892 * 893 * Response received by host processor after RM has handled 894 * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's 895 * non-real-time register values. 896 * 897 * @hdr: Generic Header 898 * @addr_lo: Ring 32 LSBs of base address 899 * @addr_hi: Ring 16 MSBs of base address. 900 * @count: Ring number of elements. 901 * @mode: Ring mode. 902 * @size: encoded Ring element size 903 * @order_id: ing order ID. 904 */ 905 struct ti_sci_msg_rm_ring_get_cfg_resp { 906 struct ti_sci_msg_hdr hdr; 907 u32 addr_lo; 908 u32 addr_hi; 909 u32 count; 910 u8 mode; 911 u8 size; 912 u8 order_id; 913 } __packed; 914 915 /** 916 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 917 * thread 918 * @hdr: Generic Header 919 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 920 * used to pair the source and destination threads. 921 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 922 * 923 * UDMAP transmit channels mapped to source threads will have their 924 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 925 * is successful. 926 927 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 928 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 929 * the destination thread is not greater than or equal to 0x8000. 930 * 931 * UDMAP receive channels mapped to destination threads will have their 932 * RCHAN_THRD_ID register programmed with the source thread if the pairing 933 * is successful. 934 * 935 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 936 * message. 937 */ 938 struct ti_sci_msg_psil_pair { 939 struct ti_sci_msg_hdr hdr; 940 u32 nav_id; 941 u32 src_thread; 942 u32 dst_thread; 943 } __packed; 944 945 /** 946 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 947 * destination thread 948 * @hdr: Generic Header 949 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 950 * used to unpair the source and destination threads. 951 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 952 * 953 * UDMAP transmit channels mapped to source threads will have their 954 * TCHAN_THRD_ID register cleared if the unpairing is successful. 955 * 956 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 957 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 958 * the destination thread is not greater than or equal to 0x8000. 959 * 960 * UDMAP receive channels mapped to destination threads will have their 961 * RCHAN_THRD_ID register cleared if the unpairing is successful. 962 * 963 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 964 * message. 965 */ 966 struct ti_sci_msg_psil_unpair { 967 struct ti_sci_msg_hdr hdr; 968 u32 nav_id; 969 u32 src_thread; 970 u32 dst_thread; 971 } __packed; 972 973 /** 974 * Configures a Navigator Subsystem UDMAP transmit channel 975 * 976 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 977 * transmit channel. The channel index must be assigned to the host defined 978 * in the TISCI header via the RM board configuration resource assignment 979 * range list. 980 * 981 * @hdr: Generic Header 982 * 983 * @valid_params: Bitfield defining validity of tx channel configuration 984 * parameters. The tx channel configuration fields are not valid, and will not 985 * be used for ch configuration, if their corresponding valid bit is zero. 986 * Valid bit usage: 987 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 988 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 989 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 990 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 991 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 992 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 993 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 994 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 995 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 996 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 997 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 998 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 999 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 1000 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 1001 * 1002 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 1003 * 1004 * @index: UDMAP transmit channel index. 1005 * 1006 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 1007 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 1008 * register. 1009 * 1010 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 1011 * configuration to be programmed into the tx_filt_einfo field of the 1012 * channel's TCHAN_TCFG register. 1013 * 1014 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 1015 * configuration to be programmed into the tx_filt_pswords field of the 1016 * channel's TCHAN_TCFG register. 1017 * 1018 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 1019 * interpretation configuration to be programmed into the tx_atype field of 1020 * the channel's TCHAN_TCFG register. 1021 * 1022 * @tx_chan_type: UDMAP transmit channel functional channel type and work 1023 * passing mechanism configuration to be programmed into the tx_chan_type 1024 * field of the channel's TCHAN_TCFG register. 1025 * 1026 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 1027 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 1028 * TCHAN_TCFG register. 1029 * 1030 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 1031 * fetch configuration to be programmed into the tx_fetch_size field of the 1032 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 1033 * word count that can pass through the channel for any allowed descriptor type. 1034 * 1035 * @tx_credit_count: UDMAP transmit channel transfer request credit count 1036 * configuration to be programmed into the count field of the TCHAN_TCREDIT 1037 * register. Specifies how many credits for complete TRs are available. 1038 * 1039 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 1040 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 1041 * completion queue must be assigned to the host, or a subordinate of the host, 1042 * requesting configuration of the transmit channel. 1043 * 1044 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 1045 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 1046 * 1047 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 1048 * qos field of the channel's TCHAN_TPRI_CTRL register. 1049 * 1050 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 1051 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 1052 * 1053 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1054 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1055 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1056 * section of the TRM for restrictions regarding this parameter. 1057 * 1058 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1059 * configuration to be programmed into the priority field of the channel's 1060 * TCHAN_TST_SCHED register. 1061 */ 1062 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1063 struct ti_sci_msg_hdr hdr; 1064 u32 valid_params; 1065 u16 nav_id; 1066 u16 index; 1067 u8 tx_pause_on_err; 1068 u8 tx_filt_einfo; 1069 u8 tx_filt_pswords; 1070 u8 tx_atype; 1071 u8 tx_chan_type; 1072 u8 tx_supr_tdpkt; 1073 u16 tx_fetch_size; 1074 u8 tx_credit_count; 1075 u16 txcq_qnum; 1076 u8 tx_priority; 1077 u8 tx_qos; 1078 u8 tx_orderid; 1079 u16 fdepth; 1080 u8 tx_sched_priority; 1081 } __packed; 1082 1083 /** 1084 * Response to configuring a UDMAP transmit channel. 1085 * 1086 * @hdr: Standard TISCI header 1087 */ 1088 struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp { 1089 struct ti_sci_msg_hdr hdr; 1090 } __packed; 1091 1092 /** 1093 * Configures a Navigator Subsystem UDMAP receive channel 1094 * 1095 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1096 * receive channel. The channel index must be assigned to the host defined 1097 * in the TISCI header via the RM board configuration resource assignment 1098 * range list. 1099 * 1100 * @hdr: Generic Header 1101 * 1102 * @valid_params: Bitfield defining validity of rx channel configuration 1103 * parameters. 1104 * The rx channel configuration fields are not valid, and will not be used for 1105 * ch configuration, if their corresponding valid bit is zero. 1106 * Valid bit usage: 1107 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1108 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1109 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1110 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1111 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1112 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1113 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1114 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1115 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1116 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1117 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1118 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1119 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1120 * 1121 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1122 * 1123 * @index: UDMAP receive channel index. 1124 * 1125 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1126 * fetch configuration to be programmed into the rx_fetch_size field of the 1127 * channel's RCHAN_RCFG register. 1128 * 1129 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1130 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1131 * The specified completion queue must be assigned to the host, or a subordinate 1132 * of the host, requesting configuration of the receive channel. 1133 * 1134 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1135 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1136 * 1137 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1138 * qos field of the channel's RCHAN_RPRI_CTRL register. 1139 * 1140 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1141 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1142 * 1143 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1144 * configuration to be programmed into the priority field of the channel's 1145 * RCHAN_RST_SCHED register. 1146 * 1147 * @flowid_start: UDMAP receive channel additional flows starting index 1148 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1149 * register. Specifies the starting index for flow IDs the receive channel is to 1150 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1151 * set as valid and configured together. The starting flow ID set by 1152 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1153 * of flows beyond the default flows statically mapped to receive channels. 1154 * The additional flows must be assigned to the host, or a subordinate of the 1155 * host, requesting configuration of the receive channel. 1156 * 1157 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1158 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1159 * This field specifies how many flow IDs are in the additional contiguous range 1160 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1161 * set as valid and configured together. Disabling the valid_params field bit 1162 * for flowid_cnt indicates no flow IDs other than the default are to be 1163 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1164 * cannot be greater than the number of receive flows in the receive channel's 1165 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1166 * subordinate of the host, requesting configuration of the receive channel. 1167 * 1168 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1169 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1170 * register. 1171 * 1172 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1173 * interpretation configuration to be programmed into the rx_atype field of the 1174 * channel's RCHAN_RCFG register. 1175 * 1176 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1177 * mechanism configuration to be programmed into the rx_chan_type field of the 1178 * channel's RCHAN_RCFG register. 1179 * 1180 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1181 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1182 * 1183 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1184 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1185 */ 1186 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1187 struct ti_sci_msg_hdr hdr; 1188 u32 valid_params; 1189 u16 nav_id; 1190 u16 index; 1191 u16 rx_fetch_size; 1192 u16 rxcq_qnum; 1193 u8 rx_priority; 1194 u8 rx_qos; 1195 u8 rx_orderid; 1196 u8 rx_sched_priority; 1197 u16 flowid_start; 1198 u16 flowid_cnt; 1199 u8 rx_pause_on_err; 1200 u8 rx_atype; 1201 u8 rx_chan_type; 1202 u8 rx_ignore_short; 1203 u8 rx_ignore_long; 1204 } __packed; 1205 1206 /** 1207 * Response to configuring a UDMAP receive channel. 1208 * 1209 * @hdr: Standard TISCI header 1210 */ 1211 struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp { 1212 struct ti_sci_msg_hdr hdr; 1213 } __packed; 1214 1215 /** 1216 * Configures a Navigator Subsystem UDMAP receive flow 1217 * 1218 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1219 * Configuration does not include the flow registers which handle size-based 1220 * free descriptor queue routing. 1221 * 1222 * The flow index must be assigned to the host defined in the TISCI header via 1223 * the RM board configuration resource assignment range list. 1224 * 1225 * @hdr: Standard TISCI header 1226 * 1227 * @valid_params 1228 * Bitfield defining validity of rx flow configuration parameters. The 1229 * rx flow configuration fields are not valid, and will not be used for flow 1230 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1231 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1232 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1233 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1234 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1235 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1236 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1237 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1238 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1239 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1240 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1241 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1242 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1243 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1244 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1245 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1246 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1247 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1248 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1249 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1250 * 1251 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1252 * allocated 1253 * 1254 * @flow_index: UDMAP receive flow index for non-optional configuration. 1255 * 1256 * @rx_einfo_present: 1257 * UDMAP receive flow extended packet info present configuration to be 1258 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1259 * 1260 * @rx_psinfo_present: 1261 * UDMAP receive flow PS words present configuration to be programmed into the 1262 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1263 * 1264 * @rx_error_handling: 1265 * UDMAP receive flow error handling configuration to be programmed into the 1266 * rx_error_handling field of the flow's RFLOW_RFA register. 1267 * 1268 * @rx_desc_type: 1269 * UDMAP receive flow descriptor type configuration to be programmed into the 1270 * rx_desc_type field field of the flow's RFLOW_RFA register. 1271 * 1272 * @rx_sop_offset: 1273 * UDMAP receive flow start of packet offset configuration to be programmed 1274 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1275 * section of the TRM for more information on this setting. Valid values for 1276 * this field are 0-255 bytes. 1277 * 1278 * @rx_dest_qnum: 1279 * UDMAP receive flow destination queue configuration to be programmed into the 1280 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1281 * destination queue must be valid within the Navigator Subsystem and must be 1282 * owned by the host, or a subordinate of the host, requesting allocation and 1283 * configuration of the receive flow. 1284 * 1285 * @rx_src_tag_hi: 1286 * UDMAP receive flow source tag high byte constant configuration to be 1287 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1288 * See the UDMAP section of the TRM for more information on this setting. 1289 * 1290 * @rx_src_tag_lo: 1291 * UDMAP receive flow source tag low byte constant configuration to be 1292 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1293 * See the UDMAP section of the TRM for more information on this setting. 1294 * 1295 * @rx_dest_tag_hi: 1296 * UDMAP receive flow destination tag high byte constant configuration to be 1297 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1298 * See the UDMAP section of the TRM for more information on this setting. 1299 * 1300 * @rx_dest_tag_lo: 1301 * UDMAP receive flow destination tag low byte constant configuration to be 1302 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1303 * See the UDMAP section of the TRM for more information on this setting. 1304 * 1305 * @rx_src_tag_hi_sel: 1306 * UDMAP receive flow source tag high byte selector configuration to be 1307 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1308 * the UDMAP section of the TRM for more information on this setting. 1309 * 1310 * @rx_src_tag_lo_sel: 1311 * UDMAP receive flow source tag low byte selector configuration to be 1312 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1313 * the UDMAP section of the TRM for more information on this setting. 1314 * 1315 * @rx_dest_tag_hi_sel: 1316 * UDMAP receive flow destination tag high byte selector configuration to be 1317 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1318 * the UDMAP section of the TRM for more information on this setting. 1319 * 1320 * @rx_dest_tag_lo_sel: 1321 * UDMAP receive flow destination tag low byte selector configuration to be 1322 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1323 * the UDMAP section of the TRM for more information on this setting. 1324 * 1325 * @rx_fdq0_sz0_qnum: 1326 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1327 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1328 * UDMAP section of the TRM for more information on this setting. The specified 1329 * free queue must be valid within the Navigator Subsystem and must be owned 1330 * by the host, or a subordinate of the host, requesting allocation and 1331 * configuration of the receive flow. 1332 * 1333 * @rx_fdq1_qnum: 1334 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1335 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1336 * UDMAP section of the TRM for more information on this setting. The specified 1337 * free queue must be valid within the Navigator Subsystem and must be owned 1338 * by the host, or a subordinate of the host, requesting allocation and 1339 * configuration of the receive flow. 1340 * 1341 * @rx_fdq2_qnum: 1342 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1343 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1344 * UDMAP section of the TRM for more information on this setting. The specified 1345 * free queue must be valid within the Navigator Subsystem and must be owned 1346 * by the host, or a subordinate of the host, requesting allocation and 1347 * configuration of the receive flow. 1348 * 1349 * @rx_fdq3_qnum: 1350 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1351 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1352 * UDMAP section of the TRM for more information on this setting. The specified 1353 * free queue must be valid within the Navigator Subsystem and must be owned 1354 * by the host, or a subordinate of the host, requesting allocation and 1355 * configuration of the receive flow. 1356 * 1357 * @rx_ps_location: 1358 * UDMAP receive flow PS words location configuration to be programmed into the 1359 * rx_ps_location field of the flow's RFLOW_RFA register. 1360 */ 1361 struct ti_sci_msg_rm_udmap_flow_cfg_req { 1362 struct ti_sci_msg_hdr hdr; 1363 u32 valid_params; 1364 u16 nav_id; 1365 u16 flow_index; 1366 u8 rx_einfo_present; 1367 u8 rx_psinfo_present; 1368 u8 rx_error_handling; 1369 u8 rx_desc_type; 1370 u16 rx_sop_offset; 1371 u16 rx_dest_qnum; 1372 u8 rx_src_tag_hi; 1373 u8 rx_src_tag_lo; 1374 u8 rx_dest_tag_hi; 1375 u8 rx_dest_tag_lo; 1376 u8 rx_src_tag_hi_sel; 1377 u8 rx_src_tag_lo_sel; 1378 u8 rx_dest_tag_hi_sel; 1379 u8 rx_dest_tag_lo_sel; 1380 u16 rx_fdq0_sz0_qnum; 1381 u16 rx_fdq1_qnum; 1382 u16 rx_fdq2_qnum; 1383 u16 rx_fdq3_qnum; 1384 u8 rx_ps_location; 1385 } __packed; 1386 1387 /** 1388 * Response to configuring a Navigator Subsystem UDMAP receive flow 1389 * 1390 * @hdr: Standard TISCI header 1391 */ 1392 struct ti_sci_msg_rm_udmap_flow_cfg_resp { 1393 struct ti_sci_msg_hdr hdr; 1394 } __packed; 1395 1396 #define FWL_MAX_PRIVID_SLOTS 3U 1397 1398 /** 1399 * struct ti_sci_msg_fwl_set_firewall_region_req - Request for configuring the firewall permissions. 1400 * 1401 * @hdr: Generic Header 1402 * 1403 * @fwl_id: Firewall ID in question 1404 * @region: Region or channel number to set config info 1405 * This field is unused in case of a simple firewall and must be initialized 1406 * to zero. In case of a region based firewall, this field indicates the 1407 * region in question. (index starting from 0) In case of a channel based 1408 * firewall, this field indicates the channel in question (index starting 1409 * from 0) 1410 * @n_permission_regs: Number of permission registers to set 1411 * @control: Contents of the firewall CONTROL register to set 1412 * @permissions: Contents of the firewall PERMISSION register to set 1413 * @start_address: Contents of the firewall START_ADDRESS register to set 1414 * @end_address: Contents of the firewall END_ADDRESS register to set 1415 */ 1416 1417 struct ti_sci_msg_fwl_set_firewall_region_req { 1418 struct ti_sci_msg_hdr hdr; 1419 u16 fwl_id; 1420 u16 region; 1421 u32 n_permission_regs; 1422 u32 control; 1423 u32 permissions[FWL_MAX_PRIVID_SLOTS]; 1424 u64 start_address; 1425 u64 end_address; 1426 } __packed; 1427 1428 /** 1429 * struct ti_sci_msg_fwl_get_firewall_region_req - Request for retrieving the firewall permissions 1430 * 1431 * @hdr: Generic Header 1432 * 1433 * @fwl_id: Firewall ID in question 1434 * @region: Region or channel number to get config info 1435 * This field is unused in case of a simple firewall and must be initialized 1436 * to zero. In case of a region based firewall, this field indicates the 1437 * region in question (index starting from 0). In case of a channel based 1438 * firewall, this field indicates the channel in question (index starting 1439 * from 0). 1440 * @n_permission_regs: Number of permission registers to retrieve 1441 */ 1442 struct ti_sci_msg_fwl_get_firewall_region_req { 1443 struct ti_sci_msg_hdr hdr; 1444 u16 fwl_id; 1445 u16 region; 1446 u32 n_permission_regs; 1447 } __packed; 1448 1449 /** 1450 * struct ti_sci_msg_fwl_get_firewall_region_resp - Response for retrieving the firewall permissions 1451 * 1452 * @hdr: Generic Header 1453 * 1454 * @fwl_id: Firewall ID in question 1455 * @region: Region or channel number to set config info This field is 1456 * unused in case of a simple firewall and must be initialized to zero. In 1457 * case of a region based firewall, this field indicates the region in 1458 * question. (index starting from 0) In case of a channel based firewall, this 1459 * field indicates the channel in question (index starting from 0) 1460 * @n_permission_regs: Number of permission registers retrieved 1461 * @control: Contents of the firewall CONTROL register 1462 * @permissions: Contents of the firewall PERMISSION registers 1463 * @start_address: Contents of the firewall START_ADDRESS register This is not applicable for channelized firewalls. 1464 * @end_address: Contents of the firewall END_ADDRESS register This is not applicable for channelized firewalls. 1465 */ 1466 struct ti_sci_msg_fwl_get_firewall_region_resp { 1467 struct ti_sci_msg_hdr hdr; 1468 u16 fwl_id; 1469 u16 region; 1470 u32 n_permission_regs; 1471 u32 control; 1472 u32 permissions[FWL_MAX_PRIVID_SLOTS]; 1473 u64 start_address; 1474 u64 end_address; 1475 } __packed; 1476 1477 /** 1478 * struct ti_sci_msg_fwl_change_owner_info_req - Request for a firewall owner change 1479 * 1480 * @hdr: Generic Header 1481 * 1482 * @fwl_id: Firewall ID in question 1483 * @region: Region or channel number if applicable 1484 * @owner_index: New owner index to transfer ownership to 1485 */ 1486 struct ti_sci_msg_fwl_change_owner_info_req { 1487 struct ti_sci_msg_hdr hdr; 1488 u16 fwl_id; 1489 u16 region; 1490 u8 owner_index; 1491 } __packed; 1492 1493 /** 1494 * struct ti_sci_msg_fwl_change_owner_info_resp - Response for a firewall owner change 1495 * 1496 * @hdr: Generic Header 1497 * 1498 * @fwl_id: Firewall ID specified in request 1499 * @region: Region or channel number specified in request 1500 * @owner_index: Owner index specified in request 1501 * @owner_privid: New owner priv-ID returned by DMSC. 1502 * @owner_permission_bits: New owner permission bits returned by DMSC. 1503 */ 1504 struct ti_sci_msg_fwl_change_owner_info_resp { 1505 struct ti_sci_msg_hdr hdr; 1506 u16 fwl_id; 1507 u16 region; 1508 u8 owner_index; 1509 u8 owner_privid; 1510 u16 owner_permission_bits; 1511 } __packed; 1512 1513 #endif /* __TI_SCI_H */ 1514