1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019-2020 NXP
5 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <cpu_func.h>
16 #include <errno.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <part.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <dm.h>
27 #include <dm/device_compat.h>
28 #include <linux/bitops.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <sdhci.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 struct fsl_esdhc {
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 char reserved1[8]; /* reserved */
55 uint fevt; /* Force event register */
56 uint admaes; /* ADMA error status register */
57 uint adsaddrl; /* ADMA system address low register */
58 uint adsaddrh; /* ADMA system address high register */
59 char reserved2[156];
60 uint hostver; /* Host controller version register */
61 char reserved3[4]; /* reserved */
62 uint dmaerraddr; /* DMA error address register */
63 char reserved4[4]; /* reserved */
64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved5[4]; /* reserved */
66 uint hostcapblt2; /* Host controller capabilities register 2 */
67 char reserved6[8]; /* reserved */
68 uint tbctl; /* Tuning block control register */
69 char reserved7[32]; /* reserved */
70 uint sdclkctl; /* SD clock control register */
71 uint sdtimingctl; /* SD timing control register */
72 char reserved8[20]; /* reserved */
73 uint dllcfg0; /* DLL config 0 register */
74 char reserved9[12]; /* reserved */
75 uint dllstat0; /* DLL status 0 register */
76 char reserved10[664];/* reserved */
77 uint esdhcctl; /* eSDHC control register */
78 };
79
80 struct fsl_esdhc_plat {
81 struct mmc_config cfg;
82 struct mmc mmc;
83 };
84
85 /**
86 * struct fsl_esdhc_priv
87 *
88 * @esdhc_regs: registers of the sdhc controller
89 * @sdhc_clk: Current clk of the sdhc controller
90 * @bus_width: bus width, 1bit, 4bit or 8bit
91 * @cfg: mmc config
92 * @mmc: mmc
93 * Following is used when Driver Model is enabled for MMC
94 * @dev: pointer for the device
95 * @cd_gpio: gpio for card detection
96 * @wp_gpio: gpio for write protection
97 */
98 struct fsl_esdhc_priv {
99 struct fsl_esdhc *esdhc_regs;
100 unsigned int sdhc_clk;
101 bool is_sdhc_per_clk;
102 unsigned int clock;
103 #if !CONFIG_IS_ENABLED(DM_MMC)
104 struct mmc *mmc;
105 #endif
106 struct udevice *dev;
107 struct sdhci_adma_desc *adma_desc_table;
108 dma_addr_t dma_addr;
109 };
110
111 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)112 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
113 {
114 uint xfertyp = 0;
115
116 if (data) {
117 xfertyp |= XFERTYP_DPSEL;
118 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
119 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
120 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
121 xfertyp |= XFERTYP_DMAEN;
122 if (data->blocks > 1) {
123 xfertyp |= XFERTYP_MSBSEL;
124 xfertyp |= XFERTYP_BCEN;
125 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
126 xfertyp |= XFERTYP_AC12EN;
127 }
128
129 if (data->flags & MMC_DATA_READ)
130 xfertyp |= XFERTYP_DTDSEL;
131 }
132
133 if (cmd->resp_type & MMC_RSP_CRC)
134 xfertyp |= XFERTYP_CCCEN;
135 if (cmd->resp_type & MMC_RSP_OPCODE)
136 xfertyp |= XFERTYP_CICEN;
137 if (cmd->resp_type & MMC_RSP_136)
138 xfertyp |= XFERTYP_RSPTYP_136;
139 else if (cmd->resp_type & MMC_RSP_BUSY)
140 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
141 else if (cmd->resp_type & MMC_RSP_PRESENT)
142 xfertyp |= XFERTYP_RSPTYP_48;
143
144 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
145 xfertyp |= XFERTYP_CMDTYP_ABORT;
146
147 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
148 }
149
150 /*
151 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
152 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)153 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
154 struct mmc_data *data)
155 {
156 struct fsl_esdhc *regs = priv->esdhc_regs;
157 uint blocks;
158 char *buffer;
159 uint databuf;
160 uint size;
161 uint irqstat;
162 ulong start;
163
164 if (data->flags & MMC_DATA_READ) {
165 blocks = data->blocks;
166 buffer = data->dest;
167 while (blocks) {
168 start = get_timer(0);
169 size = data->blocksize;
170 irqstat = esdhc_read32(®s->irqstat);
171 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
172 if (get_timer(start) > PIO_TIMEOUT) {
173 printf("\nData Read Failed in PIO Mode.");
174 return;
175 }
176 }
177 while (size && (!(irqstat & IRQSTAT_TC))) {
178 udelay(100); /* Wait before last byte transfer complete */
179 irqstat = esdhc_read32(®s->irqstat);
180 databuf = in_le32(®s->datport);
181 *((uint *)buffer) = databuf;
182 buffer += 4;
183 size -= 4;
184 }
185 blocks--;
186 }
187 } else {
188 blocks = data->blocks;
189 buffer = (char *)data->src;
190 while (blocks) {
191 start = get_timer(0);
192 size = data->blocksize;
193 irqstat = esdhc_read32(®s->irqstat);
194 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
195 if (get_timer(start) > PIO_TIMEOUT) {
196 printf("\nData Write Failed in PIO Mode.");
197 return;
198 }
199 }
200 while (size && (!(irqstat & IRQSTAT_TC))) {
201 udelay(100); /* Wait before last byte transfer complete */
202 databuf = *((uint *)buffer);
203 buffer += 4;
204 size -= 4;
205 irqstat = esdhc_read32(®s->irqstat);
206 out_le32(®s->datport, databuf);
207 }
208 blocks--;
209 }
210 }
211 }
212
esdhc_setup_watermark_level(struct fsl_esdhc_priv * priv,struct mmc_data * data)213 static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
214 struct mmc_data *data)
215 {
216 struct fsl_esdhc *regs = priv->esdhc_regs;
217 uint wml_value = data->blocksize / 4;
218
219 if (data->flags & MMC_DATA_READ) {
220 if (wml_value > WML_RD_WML_MAX)
221 wml_value = WML_RD_WML_MAX_VAL;
222
223 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
224 } else {
225 if (wml_value > WML_WR_WML_MAX)
226 wml_value = WML_WR_WML_MAX_VAL;
227
228 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
229 wml_value << 16);
230 }
231 }
232
esdhc_setup_dma(struct fsl_esdhc_priv * priv,struct mmc_data * data)233 static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
234 {
235 uint trans_bytes = data->blocksize * data->blocks;
236 struct fsl_esdhc *regs = priv->esdhc_regs;
237 phys_addr_t adma_addr;
238 void *buf;
239
240 if (data->flags & MMC_DATA_WRITE)
241 buf = (void *)data->src;
242 else
243 buf = data->dest;
244
245 priv->dma_addr = dma_map_single(buf, trans_bytes,
246 mmc_get_dma_dir(data));
247
248 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
249 priv->adma_desc_table) {
250 debug("Using ADMA2\n");
251 /* prefer ADMA2 if it is available */
252 sdhci_prepare_adma_table(priv->adma_desc_table, data,
253 priv->dma_addr);
254
255 adma_addr = virt_to_phys(priv->adma_desc_table);
256 esdhc_write32(®s->adsaddrl, lower_32_bits(adma_addr));
257 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
258 esdhc_write32(®s->adsaddrh, upper_32_bits(adma_addr));
259 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
260 PROCTL_DMAS_ADMA2);
261 } else {
262 debug("Using SDMA\n");
263 if (upper_32_bits(priv->dma_addr))
264 printf("Cannot use 64 bit addresses with SDMA\n");
265 esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr));
266 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
267 PROCTL_DMAS_SDMA);
268 }
269
270 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
271 }
272
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)273 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
274 struct mmc_data *data)
275 {
276 int timeout;
277 bool is_write = data->flags & MMC_DATA_WRITE;
278 struct fsl_esdhc *regs = priv->esdhc_regs;
279
280 if (is_write && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
281 printf("Can not write to locked SD card.\n");
282 return -EINVAL;
283 }
284
285 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
286 esdhc_setup_watermark_level(priv, data);
287 else
288 esdhc_setup_dma(priv, data);
289
290 /* Calculate the timeout period for data transactions */
291 /*
292 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
293 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
294 * So, Number of SD Clock cycles for 0.25sec should be minimum
295 * (SD Clock/sec * 0.25 sec) SD Clock cycles
296 * = (mmc->clock * 1/4) SD Clock cycles
297 * As 1) >= 2)
298 * => (2^(timeout+13)) >= mmc->clock * 1/4
299 * Taking log2 both the sides
300 * => timeout + 13 >= log2(mmc->clock/4)
301 * Rounding up to next power of 2
302 * => timeout + 13 = log2(mmc->clock/4) + 1
303 * => timeout + 13 = fls(mmc->clock/4)
304 *
305 * However, the MMC spec "It is strongly recommended for hosts to
306 * implement more than 500ms timeout value even if the card
307 * indicates the 250ms maximum busy length." Even the previous
308 * value of 300ms is known to be insufficient for some cards.
309 * So, we use
310 * => timeout + 13 = fls(mmc->clock/2)
311 */
312 timeout = fls(mmc->clock/2);
313 timeout -= 13;
314
315 if (timeout > 14)
316 timeout = 14;
317
318 if (timeout < 0)
319 timeout = 0;
320
321 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
322 (timeout == 4 || timeout == 8 || timeout == 12))
323 timeout++;
324
325 if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
326 timeout = 0xE;
327
328 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
329
330 return 0;
331 }
332
333 /*
334 * Sends a command out on the bus. Takes the mmc pointer,
335 * a command pointer, and an optional data pointer.
336 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)337 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
338 struct mmc_cmd *cmd, struct mmc_data *data)
339 {
340 int err = 0;
341 uint xfertyp;
342 uint irqstat;
343 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
344 struct fsl_esdhc *regs = priv->esdhc_regs;
345 unsigned long start;
346
347 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
348 cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
349 return 0;
350
351 esdhc_write32(®s->irqstat, -1);
352
353 sync();
354
355 /* Wait for the bus to be idle */
356 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
357 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
358 ;
359
360 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
361 ;
362
363 /* Wait at least 8 SD clock cycles before the next command */
364 /*
365 * Note: This is way more than 8 cycles, but 1ms seems to
366 * resolve timing issues with some cards
367 */
368 udelay(1000);
369
370 /* Set up for a data transfer if we have one */
371 if (data) {
372 err = esdhc_setup_data(priv, mmc, data);
373 if(err)
374 return err;
375 }
376
377 /* Figure out the transfer arguments */
378 xfertyp = esdhc_xfertyp(cmd, data);
379
380 /* Mask all irqs */
381 esdhc_write32(®s->irqsigen, 0);
382
383 /* Send the command */
384 esdhc_write32(®s->cmdarg, cmd->cmdarg);
385 esdhc_write32(®s->xfertyp, xfertyp);
386
387 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
388 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
389 flags = IRQSTAT_BRR;
390
391 /* Wait for the command to complete */
392 start = get_timer(0);
393 while (!(esdhc_read32(®s->irqstat) & flags)) {
394 if (get_timer(start) > 1000) {
395 err = -ETIMEDOUT;
396 goto out;
397 }
398 }
399
400 irqstat = esdhc_read32(®s->irqstat);
401
402 if (irqstat & CMD_ERR) {
403 err = -ECOMM;
404 goto out;
405 }
406
407 if (irqstat & IRQSTAT_CTOE) {
408 err = -ETIMEDOUT;
409 goto out;
410 }
411
412 /* Workaround for ESDHC errata ENGcm03648 */
413 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
414 int timeout = 6000;
415
416 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
417 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
418 PRSSTAT_DAT0)) {
419 udelay(100);
420 timeout--;
421 }
422
423 if (timeout <= 0) {
424 printf("Timeout waiting for DAT0 to go high!\n");
425 err = -ETIMEDOUT;
426 goto out;
427 }
428 }
429
430 /* Copy the response to the response buffer */
431 if (cmd->resp_type & MMC_RSP_136) {
432 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
433
434 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
435 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
436 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
437 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
438 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
439 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
440 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
441 cmd->response[3] = (cmdrsp0 << 8);
442 } else
443 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
444
445 /* Wait until all of the blocks are transferred */
446 if (data) {
447 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
448 esdhc_pio_read_write(priv, data);
449 } else {
450 flags = DATA_COMPLETE;
451 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
452 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
453 flags = IRQSTAT_BRR;
454
455 do {
456 irqstat = esdhc_read32(®s->irqstat);
457
458 if (irqstat & IRQSTAT_DTOE) {
459 err = -ETIMEDOUT;
460 goto out;
461 }
462
463 if (irqstat & DATA_ERR) {
464 err = -ECOMM;
465 goto out;
466 }
467 } while ((irqstat & flags) != flags);
468
469 /*
470 * Need invalidate the dcache here again to avoid any
471 * cache-fill during the DMA operations such as the
472 * speculative pre-fetching etc.
473 */
474 dma_unmap_single(priv->dma_addr,
475 data->blocks * data->blocksize,
476 mmc_get_dma_dir(data));
477 }
478 }
479
480 out:
481 /* Reset CMD and DATA portions on error */
482 if (err) {
483 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
484 SYSCTL_RSTC);
485 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
486 ;
487
488 if (data) {
489 esdhc_write32(®s->sysctl,
490 esdhc_read32(®s->sysctl) |
491 SYSCTL_RSTD);
492 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
493 ;
494 }
495 }
496
497 esdhc_write32(®s->irqstat, -1);
498
499 return err;
500 }
501
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)502 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
503 {
504 struct fsl_esdhc *regs = priv->esdhc_regs;
505 int div = 1;
506 int pre_div = 2;
507 unsigned int sdhc_clk = priv->sdhc_clk;
508 u32 time_out;
509 u32 value;
510 uint clk;
511
512 if (clock < mmc->cfg->f_min)
513 clock = mmc->cfg->f_min;
514
515 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
516 pre_div *= 2;
517
518 while (sdhc_clk / (div * pre_div) > clock && div < 16)
519 div++;
520
521 mmc->clock = sdhc_clk / pre_div / div;
522 priv->clock = mmc->clock;
523
524 pre_div >>= 1;
525 div -= 1;
526
527 clk = (pre_div << 8) | (div << 4);
528
529 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
530
531 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
532
533 time_out = 20;
534 value = PRSSTAT_SDSTB;
535 while (!(esdhc_read32(®s->prsstat) & value)) {
536 if (time_out == 0) {
537 printf("fsl_esdhc: Internal clock never stabilised.\n");
538 break;
539 }
540 time_out--;
541 mdelay(1);
542 }
543
544 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
545 }
546
esdhc_clock_control(struct fsl_esdhc_priv * priv,bool enable)547 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
548 {
549 struct fsl_esdhc *regs = priv->esdhc_regs;
550 u32 value;
551 u32 time_out;
552
553 value = esdhc_read32(®s->sysctl);
554
555 if (enable)
556 value |= SYSCTL_CKEN;
557 else
558 value &= ~SYSCTL_CKEN;
559
560 esdhc_write32(®s->sysctl, value);
561
562 time_out = 20;
563 value = PRSSTAT_SDSTB;
564 while (!(esdhc_read32(®s->prsstat) & value)) {
565 if (time_out == 0) {
566 printf("fsl_esdhc: Internal clock never stabilised.\n");
567 break;
568 }
569 time_out--;
570 mdelay(1);
571 }
572 }
573
esdhc_flush_async_fifo(struct fsl_esdhc_priv * priv)574 static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
575 {
576 struct fsl_esdhc *regs = priv->esdhc_regs;
577 u32 time_out;
578
579 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_FAF);
580
581 time_out = 20;
582 while (esdhc_read32(®s->esdhcctl) & ESDHCCTL_FAF) {
583 if (time_out == 0) {
584 printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
585 break;
586 }
587 time_out--;
588 mdelay(1);
589 }
590 }
591
esdhc_tuning_block_enable(struct fsl_esdhc_priv * priv,bool en)592 static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
593 bool en)
594 {
595 struct fsl_esdhc *regs = priv->esdhc_regs;
596
597 esdhc_clock_control(priv, false);
598 esdhc_flush_async_fifo(priv);
599 if (en)
600 esdhc_setbits32(®s->tbctl, TBCTL_TB_EN);
601 else
602 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
603 esdhc_clock_control(priv, true);
604 }
605
esdhc_exit_hs400(struct fsl_esdhc_priv * priv)606 static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
607 {
608 struct fsl_esdhc *regs = priv->esdhc_regs;
609
610 esdhc_clrbits32(®s->sdtimingctl, FLW_CTL_BG);
611 esdhc_clrbits32(®s->sdclkctl, CMD_CLK_CTL);
612
613 esdhc_clock_control(priv, false);
614 esdhc_clrbits32(®s->tbctl, HS400_MODE);
615 esdhc_clock_control(priv, true);
616
617 esdhc_clrbits32(®s->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
618 esdhc_clrbits32(®s->tbctl, HS400_WNDW_ADJUST);
619
620 esdhc_tuning_block_enable(priv, false);
621 }
622
esdhc_set_timing(struct fsl_esdhc_priv * priv,enum bus_mode mode)623 static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
624 {
625 struct fsl_esdhc *regs = priv->esdhc_regs;
626 ulong start;
627 u32 val;
628
629 /* Exit HS400 mode before setting any other mode */
630 if (esdhc_read32(®s->tbctl) & HS400_MODE &&
631 mode != MMC_HS_400)
632 esdhc_exit_hs400(priv);
633
634 esdhc_clock_control(priv, false);
635
636 if (mode == MMC_HS_200)
637 esdhc_clrsetbits32(®s->autoc12err, UHSM_MASK,
638 UHSM_SDR104_HS200);
639 if (mode == MMC_HS_400) {
640 esdhc_setbits32(®s->tbctl, HS400_MODE);
641 esdhc_setbits32(®s->sdclkctl, CMD_CLK_CTL);
642 esdhc_clock_control(priv, true);
643
644 if (priv->clock == 200000000)
645 esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL);
646
647 esdhc_setbits32(®s->dllcfg0, DLL_ENABLE);
648
649 esdhc_setbits32(®s->dllcfg0, DLL_RESET);
650 udelay(1);
651 esdhc_clrbits32(®s->dllcfg0, DLL_RESET);
652
653 start = get_timer(0);
654 val = DLL_STS_SLV_LOCK;
655 while (!(esdhc_read32(®s->dllstat0) & val)) {
656 if (get_timer(start) > 1000) {
657 printf("fsl_esdhc: delay chain lock timeout\n");
658 return -ETIMEDOUT;
659 }
660 }
661
662 esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST);
663
664 esdhc_clock_control(priv, false);
665 esdhc_flush_async_fifo(priv);
666 }
667 esdhc_clock_control(priv, true);
668 return 0;
669 }
670
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)671 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
672 {
673 struct fsl_esdhc *regs = priv->esdhc_regs;
674 int ret;
675
676 if (priv->is_sdhc_per_clk) {
677 /* Select to use peripheral clock */
678 esdhc_clock_control(priv, false);
679 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
680 esdhc_clock_control(priv, true);
681 }
682
683 if (mmc->selected_mode == MMC_HS_400)
684 esdhc_tuning_block_enable(priv, true);
685
686 /* Set the clock speed */
687 if (priv->clock != mmc->clock)
688 set_sysctl(priv, mmc, mmc->clock);
689
690 /* Set timing */
691 ret = esdhc_set_timing(priv, mmc->selected_mode);
692 if (ret)
693 return ret;
694
695 /* Set the bus width */
696 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
697
698 if (mmc->bus_width == 4)
699 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
700 else if (mmc->bus_width == 8)
701 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
702
703 return 0;
704 }
705
esdhc_enable_cache_snooping(struct fsl_esdhc * regs)706 static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
707 {
708 #ifdef CONFIG_ARCH_MPC830X
709 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
710 sysconf83xx_t *sysconf = &immr->sysconf;
711
712 setbits_be32(&sysconf->sdhccr, 0x02000000);
713 #else
714 esdhc_write32(®s->esdhcctl, 0x00000040);
715 #endif
716 }
717
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)718 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
719 {
720 struct fsl_esdhc *regs = priv->esdhc_regs;
721 ulong start;
722
723 /* Reset the entire host controller */
724 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
725
726 /* Wait until the controller is available */
727 start = get_timer(0);
728 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
729 if (get_timer(start) > 1000)
730 return -ETIMEDOUT;
731 }
732
733 /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
734 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
735
736 esdhc_enable_cache_snooping(regs);
737
738 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
739
740 /* Set the initial clock speed */
741 set_sysctl(priv, mmc, 400000);
742
743 /* Disable the BRR and BWR bits in IRQSTAT */
744 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
745
746 /* Put the PROCTL reg back to the default */
747 esdhc_write32(®s->proctl, PROCTL_INIT);
748
749 /* Set timout to the maximum value */
750 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
751
752 return 0;
753 }
754
esdhc_getcd_common(struct fsl_esdhc_priv * priv)755 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
756 {
757 struct fsl_esdhc *regs = priv->esdhc_regs;
758
759 #ifdef CONFIG_ESDHC_DETECT_QUIRK
760 if (CONFIG_ESDHC_DETECT_QUIRK)
761 return 1;
762 #endif
763 if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
764 return 1;
765
766 return 0;
767 }
768
fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv * priv,struct mmc_config * cfg)769 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
770 struct mmc_config *cfg)
771 {
772 struct fsl_esdhc *regs = priv->esdhc_regs;
773 u32 caps;
774
775 caps = esdhc_read32(®s->hostcapblt);
776 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
777 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
778 if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
779 caps |= HOSTCAPBLT_VS33;
780 if (caps & HOSTCAPBLT_VS18)
781 cfg->voltages |= MMC_VDD_165_195;
782 if (caps & HOSTCAPBLT_VS30)
783 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
784 if (caps & HOSTCAPBLT_VS33)
785 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
786
787 cfg->name = "FSL_SDHC";
788
789 if (caps & HOSTCAPBLT_HSS)
790 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
791
792 cfg->f_min = 400000;
793 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
794 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
795 }
796
797 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)798 __weak int esdhc_status_fixup(void *blob, const char *compat)
799 {
800 if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
801 do_fixup_by_compat(blob, compat, "status", "disabled",
802 sizeof("disabled"), 1);
803 return 1;
804 }
805
806 return 0;
807 }
808
809
810 #if CONFIG_IS_ENABLED(DM_MMC)
811 static int fsl_esdhc_get_cd(struct udevice *dev);
esdhc_disable_for_no_card(void * blob)812 static void esdhc_disable_for_no_card(void *blob)
813 {
814 struct udevice *dev;
815
816 for (uclass_first_device(UCLASS_MMC, &dev);
817 dev;
818 uclass_next_device(&dev)) {
819 char esdhc_path[50];
820
821 if (fsl_esdhc_get_cd(dev))
822 continue;
823
824 snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
825 (unsigned long)dev_read_addr(dev));
826 do_fixup_by_path(blob, esdhc_path, "status", "disabled",
827 sizeof("disabled"), 1);
828 }
829 }
830 #else
esdhc_disable_for_no_card(void * blob)831 static void esdhc_disable_for_no_card(void *blob)
832 {
833 }
834 #endif
835
fdt_fixup_esdhc(void * blob,struct bd_info * bd)836 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
837 {
838 const char *compat = "fsl,esdhc";
839
840 if (esdhc_status_fixup(blob, compat))
841 return;
842
843 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
844 esdhc_disable_for_no_card(blob);
845
846 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
847 gd->arch.sdhc_clk, 1);
848 }
849 #endif
850
851 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)852 static int esdhc_getcd(struct mmc *mmc)
853 {
854 struct fsl_esdhc_priv *priv = mmc->priv;
855
856 return esdhc_getcd_common(priv);
857 }
858
esdhc_init(struct mmc * mmc)859 static int esdhc_init(struct mmc *mmc)
860 {
861 struct fsl_esdhc_priv *priv = mmc->priv;
862
863 return esdhc_init_common(priv, mmc);
864 }
865
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)866 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
867 struct mmc_data *data)
868 {
869 struct fsl_esdhc_priv *priv = mmc->priv;
870
871 return esdhc_send_cmd_common(priv, mmc, cmd, data);
872 }
873
esdhc_set_ios(struct mmc * mmc)874 static int esdhc_set_ios(struct mmc *mmc)
875 {
876 struct fsl_esdhc_priv *priv = mmc->priv;
877
878 return esdhc_set_ios_common(priv, mmc);
879 }
880
881 static const struct mmc_ops esdhc_ops = {
882 .getcd = esdhc_getcd,
883 .init = esdhc_init,
884 .send_cmd = esdhc_send_cmd,
885 .set_ios = esdhc_set_ios,
886 };
887
fsl_esdhc_initialize(struct bd_info * bis,struct fsl_esdhc_cfg * cfg)888 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
889 {
890 struct fsl_esdhc_plat *plat;
891 struct fsl_esdhc_priv *priv;
892 struct mmc_config *mmc_cfg;
893 struct mmc *mmc;
894
895 if (!cfg)
896 return -EINVAL;
897
898 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
899 if (!priv)
900 return -ENOMEM;
901 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
902 if (!plat) {
903 free(priv);
904 return -ENOMEM;
905 }
906
907 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
908 priv->sdhc_clk = cfg->sdhc_clk;
909 if (gd->arch.sdhc_per_clk)
910 priv->is_sdhc_per_clk = true;
911
912 mmc_cfg = &plat->cfg;
913
914 if (cfg->max_bus_width == 8) {
915 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
916 MMC_MODE_8BIT;
917 } else if (cfg->max_bus_width == 4) {
918 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
919 } else if (cfg->max_bus_width == 1) {
920 mmc_cfg->host_caps |= MMC_MODE_1BIT;
921 } else {
922 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
923 MMC_MODE_8BIT;
924 printf("No max bus width provided. Assume 8-bit supported.\n");
925 }
926
927 if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
928 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
929
930 mmc_cfg->ops = &esdhc_ops;
931
932 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
933
934 mmc = mmc_create(mmc_cfg, priv);
935 if (!mmc)
936 return -EIO;
937
938 priv->mmc = mmc;
939 return 0;
940 }
941
fsl_esdhc_mmc_init(struct bd_info * bis)942 int fsl_esdhc_mmc_init(struct bd_info *bis)
943 {
944 struct fsl_esdhc_cfg *cfg;
945
946 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
947 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
948 /* Prefer peripheral clock which provides higher frequency. */
949 if (gd->arch.sdhc_per_clk)
950 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
951 else
952 cfg->sdhc_clk = gd->arch.sdhc_clk;
953 return fsl_esdhc_initialize(bis, cfg);
954 }
955 #else /* DM_MMC */
fsl_esdhc_probe(struct udevice * dev)956 static int fsl_esdhc_probe(struct udevice *dev)
957 {
958 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
959 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
960 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
961 u32 caps, hostver;
962 fdt_addr_t addr;
963 struct mmc *mmc;
964 int ret;
965
966 addr = dev_read_addr(dev);
967 if (addr == FDT_ADDR_T_NONE)
968 return -EINVAL;
969 #ifdef CONFIG_PPC
970 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
971 #else
972 priv->esdhc_regs = (struct fsl_esdhc *)addr;
973 #endif
974 priv->dev = dev;
975
976 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
977 /*
978 * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
979 * is set in the host capabilities register.
980 */
981 caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
982 hostver = esdhc_read32(&priv->esdhc_regs->hostver);
983 if (caps & HOSTCAPBLT_DMAS &&
984 HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
985 priv->adma_desc_table = sdhci_adma_init();
986 if (!priv->adma_desc_table)
987 debug("Could not allocate ADMA tables, falling back to SDMA\n");
988 }
989 }
990
991 if (gd->arch.sdhc_per_clk) {
992 priv->sdhc_clk = gd->arch.sdhc_per_clk;
993 priv->is_sdhc_per_clk = true;
994 } else {
995 priv->sdhc_clk = gd->arch.sdhc_clk;
996 }
997
998 if (priv->sdhc_clk <= 0) {
999 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1000 return -EINVAL;
1001 }
1002
1003 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
1004
1005 mmc_of_parse(dev, &plat->cfg);
1006
1007 mmc = &plat->mmc;
1008 mmc->cfg = &plat->cfg;
1009 mmc->dev = dev;
1010
1011 upriv->mmc = mmc;
1012
1013 ret = esdhc_init_common(priv, mmc);
1014 if (ret)
1015 return ret;
1016
1017 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
1018 !fsl_esdhc_get_cd(dev))
1019 esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
1020
1021 return 0;
1022 }
1023
fsl_esdhc_get_cd(struct udevice * dev)1024 static int fsl_esdhc_get_cd(struct udevice *dev)
1025 {
1026 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1027 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1028
1029 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
1030 return 1;
1031
1032 return esdhc_getcd_common(priv);
1033 }
1034
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1035 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1036 struct mmc_data *data)
1037 {
1038 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1039 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1040
1041 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1042 }
1043
fsl_esdhc_set_ios(struct udevice * dev)1044 static int fsl_esdhc_set_ios(struct udevice *dev)
1045 {
1046 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1047 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1048
1049 return esdhc_set_ios_common(priv, &plat->mmc);
1050 }
1051
fsl_esdhc_reinit(struct udevice * dev)1052 static int fsl_esdhc_reinit(struct udevice *dev)
1053 {
1054 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1055 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1056
1057 return esdhc_init_common(priv, &plat->mmc);
1058 }
1059
1060 #ifdef MMC_SUPPORTS_TUNING
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)1061 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
1062 {
1063 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1064 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1065 struct fsl_esdhc *regs = priv->esdhc_regs;
1066 u32 val, irqstaten;
1067 int i;
1068
1069 esdhc_tuning_block_enable(priv, true);
1070 esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING);
1071
1072 irqstaten = esdhc_read32(®s->irqstaten);
1073 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
1074
1075 for (i = 0; i < MAX_TUNING_LOOP; i++) {
1076 mmc_send_tuning(&plat->mmc, opcode, NULL);
1077 mdelay(1);
1078
1079 val = esdhc_read32(®s->autoc12err);
1080 if (!(val & EXECUTE_TUNING)) {
1081 if (val & SMPCLKSEL)
1082 break;
1083 }
1084 }
1085
1086 esdhc_write32(®s->irqstaten, irqstaten);
1087
1088 if (i != MAX_TUNING_LOOP) {
1089 if (plat->mmc.hs400_tuning)
1090 esdhc_setbits32(®s->sdtimingctl, FLW_CTL_BG);
1091 return 0;
1092 }
1093
1094 printf("fsl_esdhc: tuning failed!\n");
1095 esdhc_clrbits32(®s->autoc12err, SMPCLKSEL);
1096 esdhc_clrbits32(®s->autoc12err, EXECUTE_TUNING);
1097 esdhc_tuning_block_enable(priv, false);
1098 return -ETIMEDOUT;
1099 }
1100 #endif
1101
fsl_esdhc_hs400_prepare_ddr(struct udevice * dev)1102 int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
1103 {
1104 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1105
1106 esdhc_tuning_block_enable(priv, false);
1107 return 0;
1108 }
1109
1110 static const struct dm_mmc_ops fsl_esdhc_ops = {
1111 .get_cd = fsl_esdhc_get_cd,
1112 .send_cmd = fsl_esdhc_send_cmd,
1113 .set_ios = fsl_esdhc_set_ios,
1114 #ifdef MMC_SUPPORTS_TUNING
1115 .execute_tuning = fsl_esdhc_execute_tuning,
1116 #endif
1117 .reinit = fsl_esdhc_reinit,
1118 .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
1119 };
1120
1121 static const struct udevice_id fsl_esdhc_ids[] = {
1122 { .compatible = "fsl,esdhc", },
1123 { /* sentinel */ }
1124 };
1125
fsl_esdhc_bind(struct udevice * dev)1126 static int fsl_esdhc_bind(struct udevice *dev)
1127 {
1128 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1129
1130 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1131 }
1132
1133 U_BOOT_DRIVER(fsl_esdhc) = {
1134 .name = "fsl-esdhc-mmc",
1135 .id = UCLASS_MMC,
1136 .of_match = fsl_esdhc_ids,
1137 .ops = &fsl_esdhc_ops,
1138 .bind = fsl_esdhc_bind,
1139 .probe = fsl_esdhc_probe,
1140 .plat_auto = sizeof(struct fsl_esdhc_plat),
1141 .priv_auto = sizeof(struct fsl_esdhc_priv),
1142 };
1143 #endif
1144