1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13 #include <config.h>
14 #include <common.h>
15 #include <command.h>
16 #include <clk.h>
17 #include <cpu_func.h>
18 #include <errno.h>
19 #include <hwconfig.h>
20 #include <log.h>
21 #include <mmc.h>
22 #include <part.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <dm/device_compat.h>
26 #include <linux/bitops.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <power/regulator.h>
30 #include <malloc.h>
31 #include <fsl_esdhc_imx.h>
32 #include <fdt_support.h>
33 #include <asm/io.h>
34 #include <dm.h>
35 #include <asm-generic/gpio.h>
36 #include <dm/pinctrl.h>
37 #include <dt-structs.h>
38 #include <mapmem.h>
39 #include <dm/ofnode.h>
40 #include <linux/iopoll.h>
41
42 #if !CONFIG_IS_ENABLED(BLK)
43 #include "mmc_private.h"
44 #endif
45
46 #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
47 #ifdef CONFIG_FSL_USDHC
48 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
49 #endif
50 #endif
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
55 IRQSTATEN_CINT | \
56 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
57 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
58 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
59 IRQSTATEN_DINT)
60 #define MAX_TUNING_LOOP 40
61 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
62
63 struct fsl_esdhc {
64 uint dsaddr; /* SDMA system address register */
65 uint blkattr; /* Block attributes register */
66 uint cmdarg; /* Command argument register */
67 uint xfertyp; /* Transfer type register */
68 uint cmdrsp0; /* Command response 0 register */
69 uint cmdrsp1; /* Command response 1 register */
70 uint cmdrsp2; /* Command response 2 register */
71 uint cmdrsp3; /* Command response 3 register */
72 uint datport; /* Buffer data port register */
73 uint prsstat; /* Present state register */
74 uint proctl; /* Protocol control register */
75 uint sysctl; /* System Control Register */
76 uint irqstat; /* Interrupt status register */
77 uint irqstaten; /* Interrupt status enable register */
78 uint irqsigen; /* Interrupt signal enable register */
79 uint autoc12err; /* Auto CMD error status register */
80 uint hostcapblt; /* Host controller capabilities register */
81 uint wml; /* Watermark level register */
82 uint mixctrl; /* For USDHC */
83 char reserved1[4]; /* reserved */
84 uint fevt; /* Force event register */
85 uint admaes; /* ADMA error status register */
86 uint adsaddr; /* ADMA system address register */
87 char reserved2[4];
88 uint dllctrl;
89 uint dllstat;
90 uint clktunectrlstatus;
91 char reserved3[4];
92 uint strobe_dllctrl;
93 uint strobe_dllstat;
94 char reserved4[72];
95 uint vendorspec;
96 uint mmcboot;
97 uint vendorspec2;
98 uint tuning_ctrl; /* on i.MX6/7/8/RT */
99 char reserved5[44];
100 uint hostver; /* Host controller version register */
101 char reserved6[4]; /* reserved */
102 uint dmaerraddr; /* DMA error address register */
103 char reserved7[4]; /* reserved */
104 uint dmaerrattr; /* DMA error attribute register */
105 char reserved8[4]; /* reserved */
106 uint hostcapblt2; /* Host controller capabilities register 2 */
107 char reserved9[8]; /* reserved */
108 uint tcr; /* Tuning control register */
109 char reserved10[28]; /* reserved */
110 uint sddirctl; /* SD direction control register */
111 char reserved11[712];/* reserved */
112 uint scr; /* eSDHC control register */
113 };
114
115 struct fsl_esdhc_plat {
116 #if CONFIG_IS_ENABLED(OF_PLATDATA)
117 /* Put this first since driver model will copy the data here */
118 struct dtd_fsl_esdhc dtplat;
119 #endif
120
121 struct mmc_config cfg;
122 struct mmc mmc;
123 };
124
125 struct esdhc_soc_data {
126 u32 flags;
127 };
128
129 /**
130 * struct fsl_esdhc_priv
131 *
132 * @esdhc_regs: registers of the sdhc controller
133 * @sdhc_clk: Current clk of the sdhc controller
134 * @bus_width: bus width, 1bit, 4bit or 8bit
135 * @cfg: mmc config
136 * @mmc: mmc
137 * Following is used when Driver Model is enabled for MMC
138 * @dev: pointer for the device
139 * @non_removable: 0: removable; 1: non-removable
140 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
141 * @wp_enable: 1: enable checking wp; 0: no check
142 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
143 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
144 * @caps: controller capabilities
145 * @tuning_step: tuning step setting in tuning_ctrl register
146 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
147 * @strobe_dll_delay_target: settings in strobe_dllctrl
148 * @signal_voltage: indicating the current voltage
149 * @cd_gpio: gpio for card detection
150 * @wp_gpio: gpio for write protection
151 */
152 struct fsl_esdhc_priv {
153 struct fsl_esdhc *esdhc_regs;
154 unsigned int sdhc_clk;
155 struct clk per_clk;
156 unsigned int clock;
157 unsigned int mode;
158 unsigned int bus_width;
159 #if !CONFIG_IS_ENABLED(BLK)
160 struct mmc *mmc;
161 #endif
162 struct udevice *dev;
163 int non_removable;
164 int broken_cd;
165 int wp_enable;
166 int vs18_enable;
167 u32 flags;
168 u32 caps;
169 u32 tuning_step;
170 u32 tuning_start_tap;
171 u32 strobe_dll_delay_target;
172 u32 signal_voltage;
173 #if CONFIG_IS_ENABLED(DM_REGULATOR)
174 struct udevice *vqmmc_dev;
175 struct udevice *vmmc_dev;
176 #endif
177 #if CONFIG_IS_ENABLED(DM_GPIO)
178 struct gpio_desc cd_gpio;
179 struct gpio_desc wp_gpio;
180 #endif
181 };
182
183 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)184 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
185 {
186 uint xfertyp = 0;
187
188 if (data) {
189 xfertyp |= XFERTYP_DPSEL;
190 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
191 xfertyp |= XFERTYP_DMAEN;
192 #endif
193 if (data->blocks > 1) {
194 xfertyp |= XFERTYP_MSBSEL;
195 xfertyp |= XFERTYP_BCEN;
196 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
197 xfertyp |= XFERTYP_AC12EN;
198 #endif
199 }
200
201 if (data->flags & MMC_DATA_READ)
202 xfertyp |= XFERTYP_DTDSEL;
203 }
204
205 if (cmd->resp_type & MMC_RSP_CRC)
206 xfertyp |= XFERTYP_CCCEN;
207 if (cmd->resp_type & MMC_RSP_OPCODE)
208 xfertyp |= XFERTYP_CICEN;
209 if (cmd->resp_type & MMC_RSP_136)
210 xfertyp |= XFERTYP_RSPTYP_136;
211 else if (cmd->resp_type & MMC_RSP_BUSY)
212 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
213 else if (cmd->resp_type & MMC_RSP_PRESENT)
214 xfertyp |= XFERTYP_RSPTYP_48;
215
216 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
217 xfertyp |= XFERTYP_CMDTYP_ABORT;
218
219 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
220 }
221
222 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
223 /*
224 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
225 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)226 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
227 struct mmc_data *data)
228 {
229 struct fsl_esdhc *regs = priv->esdhc_regs;
230 uint blocks;
231 char *buffer;
232 uint databuf;
233 uint size;
234 uint irqstat;
235 ulong start;
236
237 if (data->flags & MMC_DATA_READ) {
238 blocks = data->blocks;
239 buffer = data->dest;
240 while (blocks) {
241 start = get_timer(0);
242 size = data->blocksize;
243 irqstat = esdhc_read32(®s->irqstat);
244 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
245 if (get_timer(start) > PIO_TIMEOUT) {
246 printf("\nData Read Failed in PIO Mode.");
247 return;
248 }
249 }
250 while (size && (!(irqstat & IRQSTAT_TC))) {
251 udelay(100); /* Wait before last byte transfer complete */
252 irqstat = esdhc_read32(®s->irqstat);
253 databuf = in_le32(®s->datport);
254 *((uint *)buffer) = databuf;
255 buffer += 4;
256 size -= 4;
257 }
258 blocks--;
259 }
260 } else {
261 blocks = data->blocks;
262 buffer = (char *)data->src;
263 while (blocks) {
264 start = get_timer(0);
265 size = data->blocksize;
266 irqstat = esdhc_read32(®s->irqstat);
267 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
268 if (get_timer(start) > PIO_TIMEOUT) {
269 printf("\nData Write Failed in PIO Mode.");
270 return;
271 }
272 }
273 while (size && (!(irqstat & IRQSTAT_TC))) {
274 udelay(100); /* Wait before last byte transfer complete */
275 databuf = *((uint *)buffer);
276 buffer += 4;
277 size -= 4;
278 irqstat = esdhc_read32(®s->irqstat);
279 out_le32(®s->datport, databuf);
280 }
281 blocks--;
282 }
283 }
284 }
285 #endif
286
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)287 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
288 struct mmc_data *data)
289 {
290 int timeout;
291 struct fsl_esdhc *regs = priv->esdhc_regs;
292 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
293 dma_addr_t addr;
294 #endif
295 uint wml_value;
296
297 wml_value = data->blocksize/4;
298
299 if (data->flags & MMC_DATA_READ) {
300 if (wml_value > WML_RD_WML_MAX)
301 wml_value = WML_RD_WML_MAX_VAL;
302
303 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
304 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
305 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
306 addr = virt_to_phys((void *)(data->dest));
307 if (upper_32_bits(addr))
308 printf("Error found for upper 32 bits\n");
309 else
310 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
311 #else
312 esdhc_write32(®s->dsaddr, (u32)data->dest);
313 #endif
314 #endif
315 } else {
316 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
317 flush_dcache_range((ulong)data->src,
318 (ulong)data->src+data->blocks
319 *data->blocksize);
320 #endif
321 if (wml_value > WML_WR_WML_MAX)
322 wml_value = WML_WR_WML_MAX_VAL;
323 if (priv->wp_enable) {
324 if ((esdhc_read32(®s->prsstat) &
325 PRSSTAT_WPSPL) == 0) {
326 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
327 return -ETIMEDOUT;
328 }
329 } else {
330 #if CONFIG_IS_ENABLED(DM_GPIO)
331 if (dm_gpio_is_valid(&priv->wp_gpio) &&
332 dm_gpio_get_value(&priv->wp_gpio)) {
333 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
334 return -ETIMEDOUT;
335 }
336 #endif
337 }
338
339 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
340 wml_value << 16);
341 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
342 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
343 addr = virt_to_phys((void *)(data->src));
344 if (upper_32_bits(addr))
345 printf("Error found for upper 32 bits\n");
346 else
347 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
348 #else
349 esdhc_write32(®s->dsaddr, (u32)data->src);
350 #endif
351 #endif
352 }
353
354 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
355
356 /* Calculate the timeout period for data transactions */
357 /*
358 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
359 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
360 * So, Number of SD Clock cycles for 0.25sec should be minimum
361 * (SD Clock/sec * 0.25 sec) SD Clock cycles
362 * = (mmc->clock * 1/4) SD Clock cycles
363 * As 1) >= 2)
364 * => (2^(timeout+13)) >= mmc->clock * 1/4
365 * Taking log2 both the sides
366 * => timeout + 13 >= log2(mmc->clock/4)
367 * Rounding up to next power of 2
368 * => timeout + 13 = log2(mmc->clock/4) + 1
369 * => timeout + 13 = fls(mmc->clock/4)
370 *
371 * However, the MMC spec "It is strongly recommended for hosts to
372 * implement more than 500ms timeout value even if the card
373 * indicates the 250ms maximum busy length." Even the previous
374 * value of 300ms is known to be insufficient for some cards.
375 * So, we use
376 * => timeout + 13 = fls(mmc->clock/2)
377 */
378 timeout = fls(mmc->clock/2);
379 timeout -= 13;
380
381 if (timeout > 14)
382 timeout = 14;
383
384 if (timeout < 0)
385 timeout = 0;
386
387 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
388 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
389 timeout++;
390 #endif
391
392 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
393 timeout = 0xE;
394 #endif
395 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
396
397 return 0;
398 }
399
check_and_invalidate_dcache_range(struct mmc_cmd * cmd,struct mmc_data * data)400 static void check_and_invalidate_dcache_range
401 (struct mmc_cmd *cmd,
402 struct mmc_data *data) {
403 unsigned start = 0;
404 unsigned end = 0;
405 unsigned size = roundup(ARCH_DMA_MINALIGN,
406 data->blocks*data->blocksize);
407 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
408 dma_addr_t addr;
409
410 addr = virt_to_phys((void *)(data->dest));
411 if (upper_32_bits(addr))
412 printf("Error found for upper 32 bits\n");
413 else
414 start = lower_32_bits(addr);
415 #else
416 start = (unsigned)data->dest;
417 #endif
418 end = start + size;
419 invalidate_dcache_range(start, end);
420 }
421
422 #ifdef CONFIG_MCF5441x
423 /*
424 * Swaps 32-bit words to little-endian byte order.
425 */
sd_swap_dma_buff(struct mmc_data * data)426 static inline void sd_swap_dma_buff(struct mmc_data *data)
427 {
428 int i, size = data->blocksize >> 2;
429 u32 *buffer = (u32 *)data->dest;
430 u32 sw;
431
432 while (data->blocks--) {
433 for (i = 0; i < size; i++) {
434 sw = __sw32(*buffer);
435 *buffer++ = sw;
436 }
437 }
438 }
439 #endif
440
441 /*
442 * Sends a command out on the bus. Takes the mmc pointer,
443 * a command pointer, and an optional data pointer.
444 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)445 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
446 struct mmc_cmd *cmd, struct mmc_data *data)
447 {
448 int err = 0;
449 uint xfertyp;
450 uint irqstat;
451 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
452 struct fsl_esdhc *regs = priv->esdhc_regs;
453 unsigned long start;
454
455 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
456 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
457 return 0;
458 #endif
459
460 esdhc_write32(®s->irqstat, -1);
461
462 sync();
463
464 /* Wait for the bus to be idle */
465 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
466 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
467 ;
468
469 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
470 ;
471
472 /* Set up for a data transfer if we have one */
473 if (data) {
474 err = esdhc_setup_data(priv, mmc, data);
475 if(err)
476 return err;
477
478 if (data->flags & MMC_DATA_READ)
479 check_and_invalidate_dcache_range(cmd, data);
480 }
481
482 /* Figure out the transfer arguments */
483 xfertyp = esdhc_xfertyp(cmd, data);
484
485 /* Mask all irqs */
486 esdhc_write32(®s->irqsigen, 0);
487
488 /* Send the command */
489 esdhc_write32(®s->cmdarg, cmd->cmdarg);
490 #if defined(CONFIG_FSL_USDHC)
491 esdhc_write32(®s->mixctrl,
492 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
493 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
494 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
495 #else
496 esdhc_write32(®s->xfertyp, xfertyp);
497 #endif
498
499 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
500 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
501 flags = IRQSTAT_BRR;
502
503 /* Wait for the command to complete */
504 start = get_timer(0);
505 while (!(esdhc_read32(®s->irqstat) & flags)) {
506 if (get_timer(start) > 1000) {
507 err = -ETIMEDOUT;
508 goto out;
509 }
510 }
511
512 irqstat = esdhc_read32(®s->irqstat);
513
514 if (irqstat & CMD_ERR) {
515 err = -ECOMM;
516 goto out;
517 }
518
519 if (irqstat & IRQSTAT_CTOE) {
520 err = -ETIMEDOUT;
521 goto out;
522 }
523
524 /* Switch voltage to 1.8V if CMD11 succeeded */
525 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
526 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
527
528 printf("Run CMD11 1.8V switch\n");
529 /* Sleep for 5 ms - max time for card to switch to 1.8V */
530 udelay(5000);
531 }
532
533 /* Workaround for ESDHC errata ENGcm03648 */
534 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
535 int timeout = 50000;
536
537 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
538 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
539 PRSSTAT_DAT0)) {
540 udelay(100);
541 timeout--;
542 }
543
544 if (timeout <= 0) {
545 printf("Timeout waiting for DAT0 to go high!\n");
546 err = -ETIMEDOUT;
547 goto out;
548 }
549 }
550
551 /* Copy the response to the response buffer */
552 if (cmd->resp_type & MMC_RSP_136) {
553 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
554
555 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
556 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
557 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
558 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
559 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
560 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
561 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
562 cmd->response[3] = (cmdrsp0 << 8);
563 } else
564 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
565
566 /* Wait until all of the blocks are transferred */
567 if (data) {
568 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
569 esdhc_pio_read_write(priv, data);
570 #else
571 flags = DATA_COMPLETE;
572 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
573 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
574 flags = IRQSTAT_BRR;
575 }
576
577 do {
578 irqstat = esdhc_read32(®s->irqstat);
579
580 if (irqstat & IRQSTAT_DTOE) {
581 err = -ETIMEDOUT;
582 goto out;
583 }
584
585 if (irqstat & DATA_ERR) {
586 err = -ECOMM;
587 goto out;
588 }
589 } while ((irqstat & flags) != flags);
590
591 /*
592 * Need invalidate the dcache here again to avoid any
593 * cache-fill during the DMA operations such as the
594 * speculative pre-fetching etc.
595 */
596 if (data->flags & MMC_DATA_READ) {
597 check_and_invalidate_dcache_range(cmd, data);
598 #ifdef CONFIG_MCF5441x
599 sd_swap_dma_buff(data);
600 #endif
601 }
602 #endif
603 }
604
605 out:
606 /* Reset CMD and DATA portions on error */
607 if (err) {
608 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
609 SYSCTL_RSTC);
610 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
611 ;
612
613 if (data) {
614 esdhc_write32(®s->sysctl,
615 esdhc_read32(®s->sysctl) |
616 SYSCTL_RSTD);
617 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
618 ;
619 }
620
621 /* If this was CMD11, then notify that power cycle is needed */
622 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
623 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
624 }
625
626 esdhc_write32(®s->irqstat, -1);
627
628 return err;
629 }
630
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)631 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
632 {
633 struct fsl_esdhc *regs = priv->esdhc_regs;
634 int div = 1;
635 u32 tmp;
636 int ret;
637 #ifdef ARCH_MXC
638 #ifdef CONFIG_MX53
639 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
640 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
641 #else
642 int pre_div = 1;
643 #endif
644 #else
645 int pre_div = 2;
646 #endif
647 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
648 int sdhc_clk = priv->sdhc_clk;
649 uint clk;
650
651 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
652 pre_div *= 2;
653
654 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
655 div++;
656
657 pre_div >>= 1;
658 div -= 1;
659
660 clk = (pre_div << 8) | (div << 4);
661
662 #ifdef CONFIG_FSL_USDHC
663 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
664 #else
665 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
666 #endif
667
668 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
669
670 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
671 if (ret)
672 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
673
674 #ifdef CONFIG_FSL_USDHC
675 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
676 #else
677 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
678 #endif
679
680 priv->clock = clock;
681 }
682
683 #ifdef MMC_SUPPORTS_TUNING
esdhc_change_pinstate(struct udevice * dev)684 static int esdhc_change_pinstate(struct udevice *dev)
685 {
686 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
687 int ret;
688
689 switch (priv->mode) {
690 case UHS_SDR50:
691 case UHS_DDR50:
692 ret = pinctrl_select_state(dev, "state_100mhz");
693 break;
694 case UHS_SDR104:
695 case MMC_HS_200:
696 case MMC_HS_400:
697 case MMC_HS_400_ES:
698 ret = pinctrl_select_state(dev, "state_200mhz");
699 break;
700 default:
701 ret = pinctrl_select_state(dev, "default");
702 break;
703 }
704
705 if (ret)
706 printf("%s %d error\n", __func__, priv->mode);
707
708 return ret;
709 }
710
esdhc_reset_tuning(struct mmc * mmc)711 static void esdhc_reset_tuning(struct mmc *mmc)
712 {
713 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
714 struct fsl_esdhc *regs = priv->esdhc_regs;
715
716 if (priv->flags & ESDHC_FLAG_USDHC) {
717 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
718 esdhc_clrbits32(®s->autoc12err,
719 MIX_CTRL_SMPCLK_SEL |
720 MIX_CTRL_EXE_TUNE);
721 }
722 }
723 }
724
esdhc_set_strobe_dll(struct mmc * mmc)725 static void esdhc_set_strobe_dll(struct mmc *mmc)
726 {
727 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
728 struct fsl_esdhc *regs = priv->esdhc_regs;
729 u32 val;
730
731 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
732 esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
733
734 /*
735 * enable strobe dll ctrl and adjust the delay target
736 * for the uSDHC loopback read clock
737 */
738 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
739 (priv->strobe_dll_delay_target <<
740 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
741 esdhc_write32(®s->strobe_dllctrl, val);
742 /* wait 1us to make sure strobe dll status register stable */
743 mdelay(1);
744 val = esdhc_read32(®s->strobe_dllstat);
745 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
746 pr_warn("HS400 strobe DLL status REF not lock!\n");
747 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
748 pr_warn("HS400 strobe DLL status SLV not lock!\n");
749 }
750 }
751
esdhc_set_timing(struct mmc * mmc)752 static int esdhc_set_timing(struct mmc *mmc)
753 {
754 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
755 struct fsl_esdhc *regs = priv->esdhc_regs;
756 u32 mixctrl;
757
758 mixctrl = esdhc_read32(®s->mixctrl);
759 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
760
761 switch (mmc->selected_mode) {
762 case MMC_LEGACY:
763 esdhc_reset_tuning(mmc);
764 esdhc_write32(®s->mixctrl, mixctrl);
765 break;
766 case MMC_HS_400:
767 case MMC_HS_400_ES:
768 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
769 esdhc_write32(®s->mixctrl, mixctrl);
770 break;
771 case MMC_HS:
772 case MMC_HS_52:
773 case MMC_HS_200:
774 case SD_HS:
775 case UHS_SDR12:
776 case UHS_SDR25:
777 case UHS_SDR50:
778 case UHS_SDR104:
779 esdhc_write32(®s->mixctrl, mixctrl);
780 break;
781 case UHS_DDR50:
782 case MMC_DDR_52:
783 mixctrl |= MIX_CTRL_DDREN;
784 esdhc_write32(®s->mixctrl, mixctrl);
785 break;
786 default:
787 printf("Not supported %d\n", mmc->selected_mode);
788 return -EINVAL;
789 }
790
791 priv->mode = mmc->selected_mode;
792
793 return esdhc_change_pinstate(mmc->dev);
794 }
795
esdhc_set_voltage(struct mmc * mmc)796 static int esdhc_set_voltage(struct mmc *mmc)
797 {
798 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
799 struct fsl_esdhc *regs = priv->esdhc_regs;
800 #if CONFIG_IS_ENABLED(DM_REGULATOR)
801 int ret;
802 #endif
803
804 priv->signal_voltage = mmc->signal_voltage;
805 switch (mmc->signal_voltage) {
806 case MMC_SIGNAL_VOLTAGE_330:
807 if (priv->vs18_enable)
808 return -ENOTSUPP;
809 #if CONFIG_IS_ENABLED(DM_REGULATOR)
810 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
811 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
812 if (ret) {
813 printf("Setting to 3.3V error");
814 return -EIO;
815 }
816 /* Wait for 5ms */
817 mdelay(5);
818 }
819 #endif
820
821 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
822 if (!(esdhc_read32(®s->vendorspec) &
823 ESDHC_VENDORSPEC_VSELECT))
824 return 0;
825
826 return -EAGAIN;
827 case MMC_SIGNAL_VOLTAGE_180:
828 #if CONFIG_IS_ENABLED(DM_REGULATOR)
829 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
830 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
831 if (ret) {
832 printf("Setting to 1.8V error");
833 return -EIO;
834 }
835 }
836 #endif
837 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
838 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
839 return 0;
840
841 return -EAGAIN;
842 case MMC_SIGNAL_VOLTAGE_120:
843 return -ENOTSUPP;
844 default:
845 return 0;
846 }
847 }
848
esdhc_stop_tuning(struct mmc * mmc)849 static void esdhc_stop_tuning(struct mmc *mmc)
850 {
851 struct mmc_cmd cmd;
852
853 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
854 cmd.cmdarg = 0;
855 cmd.resp_type = MMC_RSP_R1b;
856
857 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
858 }
859
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)860 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
861 {
862 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
863 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
864 struct fsl_esdhc *regs = priv->esdhc_regs;
865 struct mmc *mmc = &plat->mmc;
866 u32 irqstaten = esdhc_read32(®s->irqstaten);
867 u32 irqsigen = esdhc_read32(®s->irqsigen);
868 int i, ret = -ETIMEDOUT;
869 u32 val, mixctrl;
870
871 /* clock tuning is not needed for upto 52MHz */
872 if (mmc->clock <= 52000000)
873 return 0;
874
875 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
876 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
877 val = esdhc_read32(®s->autoc12err);
878 mixctrl = esdhc_read32(®s->mixctrl);
879 val &= ~MIX_CTRL_SMPCLK_SEL;
880 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
881
882 val |= MIX_CTRL_EXE_TUNE;
883 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
884
885 esdhc_write32(®s->autoc12err, val);
886 esdhc_write32(®s->mixctrl, mixctrl);
887 }
888
889 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
890 mixctrl = esdhc_read32(®s->mixctrl);
891 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
892 esdhc_write32(®s->mixctrl, mixctrl);
893
894 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
895 esdhc_write32(®s->irqsigen, IRQSTATEN_BRR);
896
897 /*
898 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
899 * of loops reaches 40 times.
900 */
901 for (i = 0; i < MAX_TUNING_LOOP; i++) {
902 u32 ctrl;
903
904 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
905 if (mmc->bus_width == 8)
906 esdhc_write32(®s->blkattr, 0x7080);
907 else if (mmc->bus_width == 4)
908 esdhc_write32(®s->blkattr, 0x7040);
909 } else {
910 esdhc_write32(®s->blkattr, 0x7040);
911 }
912
913 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
914 val = esdhc_read32(®s->mixctrl);
915 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
916 esdhc_write32(®s->mixctrl, val);
917
918 /* We are using STD tuning, no need to check return value */
919 mmc_send_tuning(mmc, opcode, NULL);
920
921 ctrl = esdhc_read32(®s->autoc12err);
922 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
923 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
924 ret = 0;
925 break;
926 }
927 }
928
929 esdhc_write32(®s->irqstaten, irqstaten);
930 esdhc_write32(®s->irqsigen, irqsigen);
931
932 esdhc_stop_tuning(mmc);
933
934 return ret;
935 }
936 #endif
937
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)938 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
939 {
940 struct fsl_esdhc *regs = priv->esdhc_regs;
941 int ret __maybe_unused;
942 u32 clock;
943
944 #ifdef MMC_SUPPORTS_TUNING
945 /*
946 * call esdhc_set_timing() before update the clock rate,
947 * This is because current we support DDR and SDR mode,
948 * Once the DDR_EN bit is set, the card clock will be
949 * divide by 2 automatically. So need to do this before
950 * setting clock rate.
951 */
952 if (priv->mode != mmc->selected_mode) {
953 ret = esdhc_set_timing(mmc);
954 if (ret) {
955 printf("esdhc_set_timing error %d\n", ret);
956 return ret;
957 }
958 }
959 #endif
960
961 /* Set the clock speed */
962 clock = mmc->clock;
963 if (clock < mmc->cfg->f_min)
964 clock = mmc->cfg->f_min;
965
966 if (priv->clock != clock)
967 set_sysctl(priv, mmc, clock);
968
969 #ifdef MMC_SUPPORTS_TUNING
970 if (mmc->clk_disable) {
971 #ifdef CONFIG_FSL_USDHC
972 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
973 #else
974 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
975 #endif
976 } else {
977 #ifdef CONFIG_FSL_USDHC
978 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
979 VENDORSPEC_CKEN);
980 #else
981 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
982 #endif
983 }
984
985 /*
986 * For HS400/HS400ES mode, make sure set the strobe dll in the
987 * target clock rate. So call esdhc_set_strobe_dll() after the
988 * clock updated.
989 */
990 if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
991 esdhc_set_strobe_dll(mmc);
992
993 if (priv->signal_voltage != mmc->signal_voltage) {
994 ret = esdhc_set_voltage(mmc);
995 if (ret) {
996 if (ret != -ENOTSUPP)
997 printf("esdhc_set_voltage error %d\n", ret);
998 return ret;
999 }
1000 }
1001 #endif
1002
1003 /* Set the bus width */
1004 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1005
1006 if (mmc->bus_width == 4)
1007 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1008 else if (mmc->bus_width == 8)
1009 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1010
1011 return 0;
1012 }
1013
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)1014 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1015 {
1016 struct fsl_esdhc *regs = priv->esdhc_regs;
1017 ulong start;
1018
1019 /* Reset the entire host controller */
1020 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1021
1022 /* Wait until the controller is available */
1023 start = get_timer(0);
1024 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1025 if (get_timer(start) > 1000)
1026 return -ETIMEDOUT;
1027 }
1028
1029 #if defined(CONFIG_FSL_USDHC)
1030 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1031 esdhc_write32(®s->mmcboot, 0x0);
1032 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1033 esdhc_write32(®s->mixctrl, 0x0);
1034 esdhc_write32(®s->clktunectrlstatus, 0x0);
1035
1036 /* Put VEND_SPEC to default value */
1037 if (priv->vs18_enable)
1038 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1039 ESDHC_VENDORSPEC_VSELECT));
1040 else
1041 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1042
1043 /* Disable DLL_CTRL delay line */
1044 esdhc_write32(®s->dllctrl, 0x0);
1045 #endif
1046
1047 #ifndef ARCH_MXC
1048 /* Enable cache snooping */
1049 esdhc_write32(®s->scr, 0x00000040);
1050 #endif
1051
1052 #ifndef CONFIG_FSL_USDHC
1053 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1054 #else
1055 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1056 #endif
1057
1058 /* Set the initial clock speed */
1059 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1060
1061 /* Disable the BRR and BWR bits in IRQSTAT */
1062 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1063
1064 #ifdef CONFIG_MCF5441x
1065 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1066 #else
1067 /* Put the PROCTL reg back to the default */
1068 esdhc_write32(®s->proctl, PROCTL_INIT);
1069 #endif
1070
1071 /* Set timout to the maximum value */
1072 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1073
1074 return 0;
1075 }
1076
esdhc_getcd_common(struct fsl_esdhc_priv * priv)1077 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1078 {
1079 struct fsl_esdhc *regs = priv->esdhc_regs;
1080 int timeout = 1000;
1081
1082 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1083 if (CONFIG_ESDHC_DETECT_QUIRK)
1084 return 1;
1085 #endif
1086
1087 #if CONFIG_IS_ENABLED(DM_MMC)
1088 if (priv->non_removable)
1089 return 1;
1090
1091 if (priv->broken_cd)
1092 return 1;
1093 #if CONFIG_IS_ENABLED(DM_GPIO)
1094 if (dm_gpio_is_valid(&priv->cd_gpio))
1095 return dm_gpio_get_value(&priv->cd_gpio);
1096 #endif
1097 #endif
1098
1099 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1100 udelay(1000);
1101
1102 return timeout > 0;
1103 }
1104
esdhc_reset(struct fsl_esdhc * regs)1105 static int esdhc_reset(struct fsl_esdhc *regs)
1106 {
1107 ulong start;
1108
1109 /* reset the controller */
1110 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1111
1112 /* hardware clears the bit when it is done */
1113 start = get_timer(0);
1114 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1115 if (get_timer(start) > 100) {
1116 printf("MMC/SD: Reset never completed.\n");
1117 return -ETIMEDOUT;
1118 }
1119 }
1120
1121 return 0;
1122 }
1123
1124 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)1125 static int esdhc_getcd(struct mmc *mmc)
1126 {
1127 struct fsl_esdhc_priv *priv = mmc->priv;
1128
1129 return esdhc_getcd_common(priv);
1130 }
1131
esdhc_init(struct mmc * mmc)1132 static int esdhc_init(struct mmc *mmc)
1133 {
1134 struct fsl_esdhc_priv *priv = mmc->priv;
1135
1136 return esdhc_init_common(priv, mmc);
1137 }
1138
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1139 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1140 struct mmc_data *data)
1141 {
1142 struct fsl_esdhc_priv *priv = mmc->priv;
1143
1144 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1145 }
1146
esdhc_set_ios(struct mmc * mmc)1147 static int esdhc_set_ios(struct mmc *mmc)
1148 {
1149 struct fsl_esdhc_priv *priv = mmc->priv;
1150
1151 return esdhc_set_ios_common(priv, mmc);
1152 }
1153
1154 static const struct mmc_ops esdhc_ops = {
1155 .getcd = esdhc_getcd,
1156 .init = esdhc_init,
1157 .send_cmd = esdhc_send_cmd,
1158 .set_ios = esdhc_set_ios,
1159 };
1160 #endif
1161
fsl_esdhc_init(struct fsl_esdhc_priv * priv,struct fsl_esdhc_plat * plat)1162 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1163 struct fsl_esdhc_plat *plat)
1164 {
1165 struct mmc_config *cfg;
1166 struct fsl_esdhc *regs;
1167 u32 caps, voltage_caps;
1168 int ret;
1169
1170 if (!priv)
1171 return -EINVAL;
1172
1173 regs = priv->esdhc_regs;
1174
1175 /* First reset the eSDHC controller */
1176 ret = esdhc_reset(regs);
1177 if (ret)
1178 return ret;
1179
1180 #ifdef CONFIG_MCF5441x
1181 /* ColdFire, using SDHC_DATA[3] for card detection */
1182 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1183 #endif
1184
1185 #ifndef CONFIG_FSL_USDHC
1186 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1187 | SYSCTL_IPGEN | SYSCTL_CKEN);
1188 /* Clearing tuning bits in case ROM has set it already */
1189 esdhc_write32(®s->mixctrl, 0);
1190 esdhc_write32(®s->autoc12err, 0);
1191 esdhc_write32(®s->clktunectrlstatus, 0);
1192 #else
1193 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1194 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1195 #endif
1196
1197 if (priv->vs18_enable)
1198 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1199
1200 esdhc_write32(®s->irqstaten, SDHCI_IRQ_EN_BITS);
1201 cfg = &plat->cfg;
1202 #ifndef CONFIG_DM_MMC
1203 memset(cfg, '\0', sizeof(*cfg));
1204 #endif
1205
1206 voltage_caps = 0;
1207 caps = esdhc_read32(®s->hostcapblt);
1208
1209 #ifdef CONFIG_MCF5441x
1210 /*
1211 * MCF5441x RM declares in more points that sdhc clock speed must
1212 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1213 * from host capabilities.
1214 */
1215 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1216 #endif
1217
1218 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1219 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1220 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1221 #endif
1222
1223 /* T4240 host controller capabilities register should have VS33 bit */
1224 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1225 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1226 #endif
1227
1228 if (caps & ESDHC_HOSTCAPBLT_VS18)
1229 voltage_caps |= MMC_VDD_165_195;
1230 if (caps & ESDHC_HOSTCAPBLT_VS30)
1231 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1232 if (caps & ESDHC_HOSTCAPBLT_VS33)
1233 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1234
1235 cfg->name = "FSL_SDHC";
1236 #if !CONFIG_IS_ENABLED(DM_MMC)
1237 cfg->ops = &esdhc_ops;
1238 #endif
1239 #ifdef CONFIG_SYS_SD_VOLTAGE
1240 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1241 #else
1242 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1243 #endif
1244 if ((cfg->voltages & voltage_caps) == 0) {
1245 printf("voltage not supported by controller\n");
1246 return -1;
1247 }
1248
1249 if (priv->bus_width == 8)
1250 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1251 else if (priv->bus_width == 4)
1252 cfg->host_caps = MMC_MODE_4BIT;
1253
1254 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1255 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1256 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1257 #endif
1258
1259 if (priv->bus_width > 0) {
1260 if (priv->bus_width < 8)
1261 cfg->host_caps &= ~MMC_MODE_8BIT;
1262 if (priv->bus_width < 4)
1263 cfg->host_caps &= ~MMC_MODE_4BIT;
1264 }
1265
1266 if (caps & ESDHC_HOSTCAPBLT_HSS)
1267 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1268
1269 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1270 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1271 cfg->host_caps &= ~MMC_MODE_8BIT;
1272 #endif
1273
1274 cfg->host_caps |= priv->caps;
1275
1276 cfg->f_min = 400000;
1277 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1278
1279 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1280
1281 esdhc_write32(®s->dllctrl, 0);
1282 if (priv->flags & ESDHC_FLAG_USDHC) {
1283 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1284 u32 val = esdhc_read32(®s->tuning_ctrl);
1285
1286 val |= ESDHC_STD_TUNING_EN;
1287 val &= ~ESDHC_TUNING_START_TAP_MASK;
1288 val |= priv->tuning_start_tap;
1289 val &= ~ESDHC_TUNING_STEP_MASK;
1290 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1291
1292 /* Disable the CMD CRC check for tuning, if not, need to
1293 * add some delay after every tuning command, because
1294 * hardware standard tuning logic will directly go to next
1295 * step once it detect the CMD CRC error, will not wait for
1296 * the card side to finally send out the tuning data, trigger
1297 * the buffer read ready interrupt immediately. If usdhc send
1298 * the next tuning command some eMMC card will stuck, can't
1299 * response, block the tuning procedure or the first command
1300 * after the whole tuning procedure always can't get any response.
1301 */
1302 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1303 esdhc_write32(®s->tuning_ctrl, val);
1304 }
1305 }
1306
1307 return 0;
1308 }
1309
1310 #if !CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg * cfg,struct fsl_esdhc_priv * priv)1311 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1312 struct fsl_esdhc_priv *priv)
1313 {
1314 if (!cfg || !priv)
1315 return -EINVAL;
1316
1317 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1318 priv->bus_width = cfg->max_bus_width;
1319 priv->sdhc_clk = cfg->sdhc_clk;
1320 priv->wp_enable = cfg->wp_enable;
1321 priv->vs18_enable = cfg->vs18_enable;
1322
1323 return 0;
1324 };
1325
fsl_esdhc_initialize(struct bd_info * bis,struct fsl_esdhc_cfg * cfg)1326 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
1327 {
1328 struct fsl_esdhc_plat *plat;
1329 struct fsl_esdhc_priv *priv;
1330 struct mmc *mmc;
1331 int ret;
1332
1333 if (!cfg)
1334 return -EINVAL;
1335
1336 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1337 if (!priv)
1338 return -ENOMEM;
1339 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1340 if (!plat) {
1341 free(priv);
1342 return -ENOMEM;
1343 }
1344
1345 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1346 if (ret) {
1347 debug("%s xlate failure\n", __func__);
1348 free(plat);
1349 free(priv);
1350 return ret;
1351 }
1352
1353 ret = fsl_esdhc_init(priv, plat);
1354 if (ret) {
1355 debug("%s init failure\n", __func__);
1356 free(plat);
1357 free(priv);
1358 return ret;
1359 }
1360
1361 mmc = mmc_create(&plat->cfg, priv);
1362 if (!mmc)
1363 return -EIO;
1364
1365 priv->mmc = mmc;
1366
1367 return 0;
1368 }
1369
fsl_esdhc_mmc_init(struct bd_info * bis)1370 int fsl_esdhc_mmc_init(struct bd_info *bis)
1371 {
1372 struct fsl_esdhc_cfg *cfg;
1373
1374 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1375 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1376 cfg->sdhc_clk = gd->arch.sdhc_clk;
1377 return fsl_esdhc_initialize(bis, cfg);
1378 }
1379 #endif
1380
1381 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)1382 __weak int esdhc_status_fixup(void *blob, const char *compat)
1383 {
1384 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1385 if (!hwconfig("esdhc")) {
1386 do_fixup_by_compat(blob, compat, "status", "disabled",
1387 sizeof("disabled"), 1);
1388 return 1;
1389 }
1390 #endif
1391 return 0;
1392 }
1393
fdt_fixup_esdhc(void * blob,struct bd_info * bd)1394 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
1395 {
1396 const char *compat = "fsl,esdhc";
1397
1398 if (esdhc_status_fixup(blob, compat))
1399 return;
1400
1401 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1402 gd->arch.sdhc_clk, 1);
1403 }
1404 #endif
1405
1406 #if CONFIG_IS_ENABLED(DM_MMC)
1407 #include <asm/arch/clock.h>
init_clk_usdhc(u32 index)1408 __weak void init_clk_usdhc(u32 index)
1409 {
1410 }
1411
fsl_esdhc_of_to_plat(struct udevice * dev)1412 static int fsl_esdhc_of_to_plat(struct udevice *dev)
1413 {
1414 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1415 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1416 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1417 struct udevice *vqmmc_dev;
1418 int ret;
1419 #endif
1420 const void *fdt = gd->fdt_blob;
1421 int node = dev_of_offset(dev);
1422
1423 fdt_addr_t addr;
1424 unsigned int val;
1425
1426 addr = dev_read_addr(dev);
1427 if (addr == FDT_ADDR_T_NONE)
1428 return -EINVAL;
1429 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1430 priv->dev = dev;
1431 priv->mode = -1;
1432
1433 val = dev_read_u32_default(dev, "bus-width", -1);
1434 if (val == 8)
1435 priv->bus_width = 8;
1436 else if (val == 4)
1437 priv->bus_width = 4;
1438 else
1439 priv->bus_width = 1;
1440
1441 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1442 priv->tuning_step = val;
1443 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1444 ESDHC_TUNING_START_TAP_DEFAULT);
1445 priv->tuning_start_tap = val;
1446 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1447 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1448 priv->strobe_dll_delay_target = val;
1449
1450 if (dev_read_bool(dev, "broken-cd"))
1451 priv->broken_cd = 1;
1452
1453 if (dev_read_bool(dev, "non-removable")) {
1454 priv->non_removable = 1;
1455 } else {
1456 priv->non_removable = 0;
1457 #if CONFIG_IS_ENABLED(DM_GPIO)
1458 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1459 GPIOD_IS_IN);
1460 #endif
1461 }
1462
1463 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1464 priv->wp_enable = 1;
1465 } else {
1466 priv->wp_enable = 0;
1467 #if CONFIG_IS_ENABLED(DM_GPIO)
1468 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1469 GPIOD_IS_IN);
1470 #endif
1471 }
1472
1473 priv->vs18_enable = 0;
1474
1475 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1476 /*
1477 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1478 * otherwise, emmc will work abnormally.
1479 */
1480 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1481 if (ret) {
1482 dev_dbg(dev, "no vqmmc-supply\n");
1483 } else {
1484 priv->vqmmc_dev = vqmmc_dev;
1485 ret = regulator_set_enable(vqmmc_dev, true);
1486 if (ret) {
1487 dev_err(dev, "fail to enable vqmmc-supply\n");
1488 return ret;
1489 }
1490
1491 if (regulator_get_value(vqmmc_dev) == 1800000)
1492 priv->vs18_enable = 1;
1493 }
1494 #endif
1495 #endif
1496 return 0;
1497 }
1498
fsl_esdhc_probe(struct udevice * dev)1499 static int fsl_esdhc_probe(struct udevice *dev)
1500 {
1501 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1502 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1503 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1504 struct esdhc_soc_data *data =
1505 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1506 struct mmc *mmc;
1507 #if !CONFIG_IS_ENABLED(BLK)
1508 struct blk_desc *bdesc;
1509 #endif
1510 int ret;
1511
1512 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1513 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1514 unsigned int val;
1515
1516 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1517 val = plat->dtplat.bus_width;
1518 if (val == 8)
1519 priv->bus_width = 8;
1520 else if (val == 4)
1521 priv->bus_width = 4;
1522 else
1523 priv->bus_width = 1;
1524
1525 if (dtplat->non_removable)
1526 priv->non_removable = 1;
1527 else
1528 priv->non_removable = 0;
1529
1530 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1531 struct udevice *gpiodev;
1532
1533 ret = device_get_by_driver_info_idx(dtplat->cd_gpios->idx,
1534 &gpiodev);
1535 if (ret)
1536 return ret;
1537
1538 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1539 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1540 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1541
1542 if (ret)
1543 return ret;
1544 }
1545 #endif
1546
1547 if (data)
1548 priv->flags = data->flags;
1549
1550 /*
1551 * TODO:
1552 * Because lack of clk driver, if SDHC clk is not enabled,
1553 * need to enable it first before this driver is invoked.
1554 *
1555 * we use MXC_ESDHC_CLK to get clk freq.
1556 * If one would like to make this function work,
1557 * the aliases should be provided in dts as this:
1558 *
1559 * aliases {
1560 * mmc0 = &usdhc1;
1561 * mmc1 = &usdhc2;
1562 * mmc2 = &usdhc3;
1563 * mmc3 = &usdhc4;
1564 * };
1565 * Then if your board only supports mmc2 and mmc3, but we can
1566 * correctly get the seq as 2 and 3, then let mxc_get_clock
1567 * work as expected.
1568 */
1569
1570 init_clk_usdhc(dev_seq(dev));
1571
1572 #if CONFIG_IS_ENABLED(CLK)
1573 /* Assigned clock already set clock */
1574 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1575 if (ret) {
1576 printf("Failed to get per_clk\n");
1577 return ret;
1578 }
1579 ret = clk_enable(&priv->per_clk);
1580 if (ret) {
1581 printf("Failed to enable per_clk\n");
1582 return ret;
1583 }
1584
1585 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1586 #else
1587 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
1588 if (priv->sdhc_clk <= 0) {
1589 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1590 return -EINVAL;
1591 }
1592 #endif
1593
1594 ret = fsl_esdhc_init(priv, plat);
1595 if (ret) {
1596 dev_err(dev, "fsl_esdhc_init failure\n");
1597 return ret;
1598 }
1599
1600 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1601 ret = mmc_of_parse(dev, &plat->cfg);
1602 if (ret)
1603 return ret;
1604 #endif
1605
1606 mmc = &plat->mmc;
1607 mmc->cfg = &plat->cfg;
1608 mmc->dev = dev;
1609 #if !CONFIG_IS_ENABLED(BLK)
1610 mmc->priv = priv;
1611
1612 /* Setup dsr related values */
1613 mmc->dsr_imp = 0;
1614 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1615 /* Setup the universal parts of the block interface just once */
1616 bdesc = mmc_get_blk_desc(mmc);
1617 bdesc->if_type = IF_TYPE_MMC;
1618 bdesc->removable = 1;
1619 bdesc->devnum = mmc_get_next_devnum();
1620 bdesc->block_read = mmc_bread;
1621 bdesc->block_write = mmc_bwrite;
1622 bdesc->block_erase = mmc_berase;
1623
1624 /* setup initial part type */
1625 bdesc->part_type = mmc->cfg->part_type;
1626 mmc_list_add(mmc);
1627 #endif
1628
1629 upriv->mmc = mmc;
1630
1631 return esdhc_init_common(priv, mmc);
1632 }
1633
1634 #if CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_get_cd(struct udevice * dev)1635 static int fsl_esdhc_get_cd(struct udevice *dev)
1636 {
1637 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1638
1639 return esdhc_getcd_common(priv);
1640 }
1641
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1642 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1643 struct mmc_data *data)
1644 {
1645 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1646 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1647
1648 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1649 }
1650
fsl_esdhc_set_ios(struct udevice * dev)1651 static int fsl_esdhc_set_ios(struct udevice *dev)
1652 {
1653 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1654 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1655
1656 return esdhc_set_ios_common(priv, &plat->mmc);
1657 }
1658
1659 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
fsl_esdhc_set_enhanced_strobe(struct udevice * dev)1660 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1661 {
1662 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1663 struct fsl_esdhc *regs = priv->esdhc_regs;
1664 u32 m;
1665
1666 m = esdhc_read32(®s->mixctrl);
1667 m |= MIX_CTRL_HS400_ES;
1668 esdhc_write32(®s->mixctrl, m);
1669
1670 return 0;
1671 }
1672 #endif
1673
fsl_esdhc_wait_dat0(struct udevice * dev,int state,int timeout_us)1674 static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1675 int timeout_us)
1676 {
1677 int ret;
1678 u32 tmp;
1679 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1680 struct fsl_esdhc *regs = priv->esdhc_regs;
1681
1682 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
1683 !!(tmp & PRSSTAT_DAT0) == !!state,
1684 timeout_us);
1685 return ret;
1686 }
1687
1688 static const struct dm_mmc_ops fsl_esdhc_ops = {
1689 .get_cd = fsl_esdhc_get_cd,
1690 .send_cmd = fsl_esdhc_send_cmd,
1691 .set_ios = fsl_esdhc_set_ios,
1692 #ifdef MMC_SUPPORTS_TUNING
1693 .execute_tuning = fsl_esdhc_execute_tuning,
1694 #endif
1695 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1696 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1697 #endif
1698 .wait_dat0 = fsl_esdhc_wait_dat0,
1699 };
1700 #endif
1701
1702 static struct esdhc_soc_data usdhc_imx7d_data = {
1703 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1704 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1705 | ESDHC_FLAG_HS400,
1706 };
1707
1708 static struct esdhc_soc_data usdhc_imx8qm_data = {
1709 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1710 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1711 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1712 };
1713
1714 static const struct udevice_id fsl_esdhc_ids[] = {
1715 { .compatible = "fsl,imx51-esdhc", },
1716 { .compatible = "fsl,imx53-esdhc", },
1717 { .compatible = "fsl,imx6ul-usdhc", },
1718 { .compatible = "fsl,imx6sx-usdhc", },
1719 { .compatible = "fsl,imx6sl-usdhc", },
1720 { .compatible = "fsl,imx6q-usdhc", },
1721 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1722 { .compatible = "fsl,imx7ulp-usdhc", },
1723 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1724 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1725 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1726 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1727 { .compatible = "fsl,imxrt-usdhc", },
1728 { .compatible = "fsl,esdhc", },
1729 { /* sentinel */ }
1730 };
1731
1732 #if CONFIG_IS_ENABLED(BLK)
fsl_esdhc_bind(struct udevice * dev)1733 static int fsl_esdhc_bind(struct udevice *dev)
1734 {
1735 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1736
1737 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1738 }
1739 #endif
1740
1741 U_BOOT_DRIVER(fsl_esdhc) = {
1742 .name = "fsl_esdhc",
1743 .id = UCLASS_MMC,
1744 .of_match = fsl_esdhc_ids,
1745 .of_to_plat = fsl_esdhc_of_to_plat,
1746 .ops = &fsl_esdhc_ops,
1747 #if CONFIG_IS_ENABLED(BLK)
1748 .bind = fsl_esdhc_bind,
1749 #endif
1750 .probe = fsl_esdhc_probe,
1751 .plat_auto = sizeof(struct fsl_esdhc_plat),
1752 .priv_auto = sizeof(struct fsl_esdhc_priv),
1753 };
1754
1755 DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
1756 #endif
1757