1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
6 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11 */
12
13 #include <cpu_func.h>
14 #include <log.h>
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <common.h>
21 #include <clk.h>
22 #include <dm.h>
23 #include <fdt_support.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <malloc.h>
29 #include <miiphy.h>
30 #include <net.h>
31 #include <reset.h>
32 #include <dt-bindings/pinctrl/sun4i-a10.h>
33 #include <wait_bit.h>
34 #if CONFIG_IS_ENABLED(DM_GPIO)
35 #include <asm-generic/gpio.h>
36 #endif
37
38 #define MDIO_CMD_MII_BUSY BIT(0)
39 #define MDIO_CMD_MII_WRITE BIT(1)
40
41 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
42 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
43 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
44 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
45 #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
46 #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
47 #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
48 #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
49 #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
50
51 #define CONFIG_TX_DESCR_NUM 32
52 #define CONFIG_RX_DESCR_NUM 32
53 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
54
55 /*
56 * The datasheet says that each descriptor can transfers up to 4096 bytes
57 * But later, the register documentation reduces that value to 2048,
58 * using 2048 cause strange behaviours and even BSP driver use 2047
59 */
60 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
61
62 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
63 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
64
65 #define H3_EPHY_DEFAULT_VALUE 0x58000
66 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
67 #define H3_EPHY_ADDR_SHIFT 20
68 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
69 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
70 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
71 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
72
73 #define SC_RMII_EN BIT(13)
74 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
75 #define SC_ETCS_MASK GENMASK(1, 0)
76 #define SC_ETCS_EXT_GMII 0x1
77 #define SC_ETCS_INT_GMII 0x2
78 #define SC_ETXDC_MASK GENMASK(12, 10)
79 #define SC_ETXDC_OFFSET 10
80 #define SC_ERXDC_MASK GENMASK(9, 5)
81 #define SC_ERXDC_OFFSET 5
82
83 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
84
85 #define AHB_GATE_OFFSET_EPHY 0
86
87 /* IO mux settings */
88 #define SUN8I_IOMUX_H3 2
89 #define SUN8I_IOMUX_R40 5
90 #define SUN8I_IOMUX_H6 5
91 #define SUN8I_IOMUX_H616 2
92 #define SUN8I_IOMUX 4
93
94 /* H3/A64 EMAC Register's offset */
95 #define EMAC_CTL0 0x00
96 #define EMAC_CTL0_FULL_DUPLEX BIT(0)
97 #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
98 #define EMAC_CTL0_SPEED_10 (0x2 << 2)
99 #define EMAC_CTL0_SPEED_100 (0x3 << 2)
100 #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
101 #define EMAC_CTL1 0x04
102 #define EMAC_CTL1_SOFT_RST BIT(0)
103 #define EMAC_CTL1_BURST_LEN_SHIFT 24
104 #define EMAC_INT_STA 0x08
105 #define EMAC_INT_EN 0x0c
106 #define EMAC_TX_CTL0 0x10
107 #define EMAC_TX_CTL0_TX_EN BIT(31)
108 #define EMAC_TX_CTL1 0x14
109 #define EMAC_TX_CTL1_TX_MD BIT(1)
110 #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
111 #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
112 #define EMAC_TX_FLOW_CTL 0x1c
113 #define EMAC_TX_DMA_DESC 0x20
114 #define EMAC_RX_CTL0 0x24
115 #define EMAC_RX_CTL0_RX_EN BIT(31)
116 #define EMAC_RX_CTL1 0x28
117 #define EMAC_RX_CTL1_RX_MD BIT(1)
118 #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
119 #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
120 #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
121 #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
122 #define EMAC_RX_DMA_DESC 0x34
123 #define EMAC_MII_CMD 0x48
124 #define EMAC_MII_DATA 0x4c
125 #define EMAC_ADDR0_HIGH 0x50
126 #define EMAC_ADDR0_LOW 0x54
127 #define EMAC_TX_DMA_STA 0xb0
128 #define EMAC_TX_CUR_DESC 0xb4
129 #define EMAC_TX_CUR_BUF 0xb8
130 #define EMAC_RX_DMA_STA 0xc0
131 #define EMAC_RX_CUR_DESC 0xc4
132
133 #define EMAC_DESC_OWN_DMA BIT(31)
134 #define EMAC_DESC_LAST_DESC BIT(30)
135 #define EMAC_DESC_FIRST_DESC BIT(29)
136 #define EMAC_DESC_CHAIN_SECOND BIT(24)
137
138 #define EMAC_DESC_RX_ERROR_MASK 0x400068db
139
140 DECLARE_GLOBAL_DATA_PTR;
141
142 enum emac_variant {
143 A83T_EMAC = 1,
144 H3_EMAC,
145 A64_EMAC,
146 R40_GMAC,
147 H6_EMAC,
148 };
149
150 struct emac_dma_desc {
151 u32 status;
152 u32 ctl_size;
153 u32 buf_addr;
154 u32 next;
155 } __aligned(ARCH_DMA_MINALIGN);
156
157 struct emac_eth_dev {
158 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
159 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
160 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
161 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
162
163 u32 interface;
164 u32 phyaddr;
165 u32 link;
166 u32 speed;
167 u32 duplex;
168 u32 phy_configured;
169 u32 tx_currdescnum;
170 u32 rx_currdescnum;
171 u32 addr;
172 u32 tx_slot;
173 bool use_internal_phy;
174
175 enum emac_variant variant;
176 void *mac_reg;
177 phys_addr_t sysctl_reg;
178 struct phy_device *phydev;
179 struct mii_dev *bus;
180 struct clk tx_clk;
181 struct clk ephy_clk;
182 struct reset_ctl tx_rst;
183 struct reset_ctl ephy_rst;
184 #if CONFIG_IS_ENABLED(DM_GPIO)
185 struct gpio_desc reset_gpio;
186 #endif
187 };
188
189
190 struct sun8i_eth_pdata {
191 struct eth_pdata eth_pdata;
192 u32 reset_delays[3];
193 int tx_delay_ps;
194 int rx_delay_ps;
195 };
196
197
sun8i_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)198 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
199 {
200 struct udevice *dev = bus->priv;
201 struct emac_eth_dev *priv = dev_get_priv(dev);
202 u32 mii_cmd;
203 int ret;
204
205 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
206 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
207 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
208 MDIO_CMD_MII_PHY_ADDR_MASK;
209
210 /*
211 * The EMAC clock is either 200 or 300 MHz, so we need a divider
212 * of 128 to get the MDIO frequency below the required 2.5 MHz.
213 */
214 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
215
216 mii_cmd |= MDIO_CMD_MII_BUSY;
217
218 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
219
220 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
221 MDIO_CMD_MII_BUSY, false,
222 CONFIG_MDIO_TIMEOUT, true);
223 if (ret < 0)
224 return ret;
225
226 return readl(priv->mac_reg + EMAC_MII_DATA);
227 }
228
sun8i_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)229 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
230 u16 val)
231 {
232 struct udevice *dev = bus->priv;
233 struct emac_eth_dev *priv = dev_get_priv(dev);
234 u32 mii_cmd;
235
236 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
237 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
238 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
239 MDIO_CMD_MII_PHY_ADDR_MASK;
240
241 /*
242 * The EMAC clock is either 200 or 300 MHz, so we need a divider
243 * of 128 to get the MDIO frequency below the required 2.5 MHz.
244 */
245 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
246
247 mii_cmd |= MDIO_CMD_MII_WRITE;
248 mii_cmd |= MDIO_CMD_MII_BUSY;
249
250 writel(val, priv->mac_reg + EMAC_MII_DATA);
251 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
252
253 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
254 MDIO_CMD_MII_BUSY, false,
255 CONFIG_MDIO_TIMEOUT, true);
256 }
257
sun8i_eth_write_hwaddr(struct udevice * dev)258 static int sun8i_eth_write_hwaddr(struct udevice *dev)
259 {
260 struct emac_eth_dev *priv = dev_get_priv(dev);
261 struct eth_pdata *pdata = dev_get_plat(dev);
262 uchar *mac_id = pdata->enetaddr;
263 u32 macid_lo, macid_hi;
264
265 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
266 (mac_id[3] << 24);
267 macid_hi = mac_id[4] + (mac_id[5] << 8);
268
269 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
270 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
271
272 return 0;
273 }
274
sun8i_adjust_link(struct emac_eth_dev * priv,struct phy_device * phydev)275 static void sun8i_adjust_link(struct emac_eth_dev *priv,
276 struct phy_device *phydev)
277 {
278 u32 v;
279
280 v = readl(priv->mac_reg + EMAC_CTL0);
281
282 if (phydev->duplex)
283 v |= EMAC_CTL0_FULL_DUPLEX;
284 else
285 v &= ~EMAC_CTL0_FULL_DUPLEX;
286
287 v &= ~EMAC_CTL0_SPEED_MASK;
288
289 switch (phydev->speed) {
290 case 1000:
291 v |= EMAC_CTL0_SPEED_1000;
292 break;
293 case 100:
294 v |= EMAC_CTL0_SPEED_100;
295 break;
296 case 10:
297 v |= EMAC_CTL0_SPEED_10;
298 break;
299 }
300 writel(v, priv->mac_reg + EMAC_CTL0);
301 }
302
sun8i_emac_set_syscon_ephy(struct emac_eth_dev * priv,u32 reg)303 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
304 {
305 if (priv->use_internal_phy) {
306 /* H3 based SoC's that has an Internal 100MBit PHY
307 * needs to be configured and powered up before use
308 */
309 reg &= ~H3_EPHY_DEFAULT_MASK;
310 reg |= H3_EPHY_DEFAULT_VALUE;
311 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
312 reg &= ~H3_EPHY_SHUTDOWN;
313 return reg | H3_EPHY_SELECT;
314 }
315
316 /* This is to select External Gigabit PHY on those boards with
317 * an internal PHY. Does not hurt on other SoCs. Linux does
318 * it as well.
319 */
320 return reg & ~H3_EPHY_SELECT;
321 }
322
sun8i_emac_set_syscon(struct sun8i_eth_pdata * pdata,struct emac_eth_dev * priv)323 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
324 struct emac_eth_dev *priv)
325 {
326 u32 reg;
327
328 if (priv->variant == R40_GMAC) {
329 /* Select RGMII for R40 */
330 reg = readl(priv->sysctl_reg + 0x164);
331 reg |= SC_ETCS_INT_GMII |
332 SC_EPIT |
333 (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
334
335 writel(reg, priv->sysctl_reg + 0x164);
336 return 0;
337 }
338
339 reg = readl(priv->sysctl_reg + 0x30);
340
341 reg = sun8i_emac_set_syscon_ephy(priv, reg);
342
343 reg &= ~(SC_ETCS_MASK | SC_EPIT);
344 if (priv->variant == H3_EMAC ||
345 priv->variant == A64_EMAC ||
346 priv->variant == H6_EMAC)
347 reg &= ~SC_RMII_EN;
348
349 switch (priv->interface) {
350 case PHY_INTERFACE_MODE_MII:
351 /* default */
352 break;
353 case PHY_INTERFACE_MODE_RGMII:
354 case PHY_INTERFACE_MODE_RGMII_ID:
355 case PHY_INTERFACE_MODE_RGMII_RXID:
356 case PHY_INTERFACE_MODE_RGMII_TXID:
357 reg |= SC_EPIT | SC_ETCS_INT_GMII;
358 break;
359 case PHY_INTERFACE_MODE_RMII:
360 if (priv->variant == H3_EMAC ||
361 priv->variant == A64_EMAC ||
362 priv->variant == H6_EMAC) {
363 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
364 break;
365 }
366 /* RMII not supported on A83T */
367 default:
368 debug("%s: Invalid PHY interface\n", __func__);
369 return -EINVAL;
370 }
371
372 if (pdata->tx_delay_ps)
373 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
374 & SC_ETXDC_MASK;
375
376 if (pdata->rx_delay_ps)
377 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
378 & SC_ERXDC_MASK;
379
380 writel(reg, priv->sysctl_reg + 0x30);
381
382 return 0;
383 }
384
sun8i_phy_init(struct emac_eth_dev * priv,void * dev)385 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
386 {
387 struct phy_device *phydev;
388
389 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
390 if (!phydev)
391 return -ENODEV;
392
393 phy_connect_dev(phydev, dev);
394
395 priv->phydev = phydev;
396 phy_config(priv->phydev);
397
398 return 0;
399 }
400
401 #define cache_clean_descriptor(desc) \
402 flush_dcache_range((uintptr_t)(desc), \
403 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
404
405 #define cache_inv_descriptor(desc) \
406 invalidate_dcache_range((uintptr_t)(desc), \
407 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
408
rx_descs_init(struct emac_eth_dev * priv)409 static void rx_descs_init(struct emac_eth_dev *priv)
410 {
411 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
412 char *rxbuffs = &priv->rxbuffer[0];
413 struct emac_dma_desc *desc_p;
414 int i;
415
416 /*
417 * Make sure we don't have dirty cache lines around, which could
418 * be cleaned to DRAM *after* the MAC has already written data to it.
419 */
420 invalidate_dcache_range((uintptr_t)desc_table_p,
421 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
422 invalidate_dcache_range((uintptr_t)rxbuffs,
423 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
424
425 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
426 desc_p = &desc_table_p[i];
427 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
428 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
429 desc_p->ctl_size = CONFIG_ETH_RXSIZE;
430 desc_p->status = EMAC_DESC_OWN_DMA;
431 }
432
433 /* Correcting the last pointer of the chain */
434 desc_p->next = (uintptr_t)&desc_table_p[0];
435
436 flush_dcache_range((uintptr_t)priv->rx_chain,
437 (uintptr_t)priv->rx_chain +
438 sizeof(priv->rx_chain));
439
440 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
441 priv->rx_currdescnum = 0;
442 }
443
tx_descs_init(struct emac_eth_dev * priv)444 static void tx_descs_init(struct emac_eth_dev *priv)
445 {
446 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
447 char *txbuffs = &priv->txbuffer[0];
448 struct emac_dma_desc *desc_p;
449 int i;
450
451 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
452 desc_p = &desc_table_p[i];
453 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
454 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
455 desc_p->ctl_size = 0;
456 desc_p->status = 0;
457 }
458
459 /* Correcting the last pointer of the chain */
460 desc_p->next = (uintptr_t)&desc_table_p[0];
461
462 /* Flush the first TX buffer descriptor we will tell the MAC about. */
463 cache_clean_descriptor(desc_table_p);
464
465 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
466 priv->tx_currdescnum = 0;
467 }
468
sun8i_emac_eth_start(struct udevice * dev)469 static int sun8i_emac_eth_start(struct udevice *dev)
470 {
471 struct emac_eth_dev *priv = dev_get_priv(dev);
472 int ret;
473
474 /* Soft reset MAC */
475 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
476 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
477 EMAC_CTL1_SOFT_RST, false, 10, true);
478 if (ret) {
479 printf("%s: Timeout\n", __func__);
480 return ret;
481 }
482
483 /* Rewrite mac address after reset */
484 sun8i_eth_write_hwaddr(dev);
485
486 /* transmission starts after the full frame arrived in TX DMA FIFO */
487 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
488
489 /*
490 * RX DMA reads data from RX DMA FIFO to host memory after a
491 * complete frame has been written to RX DMA FIFO
492 */
493 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
494
495 /* DMA burst length */
496 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
497
498 /* Initialize rx/tx descriptors */
499 rx_descs_init(priv);
500 tx_descs_init(priv);
501
502 /* PHY Start Up */
503 ret = phy_startup(priv->phydev);
504 if (ret)
505 return ret;
506
507 sun8i_adjust_link(priv, priv->phydev);
508
509 /* Start RX/TX DMA */
510 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
511 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
512 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
513
514 /* Enable RX/TX */
515 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
516 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
517
518 return 0;
519 }
520
parse_phy_pins(struct udevice * dev)521 static int parse_phy_pins(struct udevice *dev)
522 {
523 int offset;
524 const char *pin_name;
525 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
526 u32 iomux;
527
528 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
529 "pinctrl-0");
530 if (offset < 0) {
531 printf("WARNING: emac: cannot find pinctrl-0 node\n");
532 return offset;
533 }
534
535 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
536 "drive-strength", ~0);
537 if (drive != ~0) {
538 if (drive <= 10)
539 drive = SUN4I_PINCTRL_10_MA;
540 else if (drive <= 20)
541 drive = SUN4I_PINCTRL_20_MA;
542 else if (drive <= 30)
543 drive = SUN4I_PINCTRL_30_MA;
544 else
545 drive = SUN4I_PINCTRL_40_MA;
546 }
547
548 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
549 pull = SUN4I_PINCTRL_PULL_UP;
550 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
551 pull = SUN4I_PINCTRL_PULL_DOWN;
552
553 /*
554 * The GPIO pinmux value is an integration choice, so depends on the
555 * SoC, not the EMAC variant.
556 */
557 if (IS_ENABLED(CONFIG_MACH_SUN8I_H3))
558 iomux = SUN8I_IOMUX_H3;
559 else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
560 iomux = SUN8I_IOMUX_R40;
561 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
562 iomux = SUN8I_IOMUX_H6;
563 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
564 iomux = SUN8I_IOMUX_H616;
565 else
566 iomux = SUN8I_IOMUX;
567
568 for (i = 0; ; i++) {
569 int pin;
570
571 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
572 "pins", i, NULL);
573 if (!pin_name)
574 break;
575
576 pin = sunxi_name_to_gpio(pin_name);
577 if (pin < 0)
578 continue;
579
580 sunxi_gpio_set_cfgpin(pin, iomux);
581
582 if (drive != ~0)
583 sunxi_gpio_set_drv(pin, drive);
584 if (pull != ~0)
585 sunxi_gpio_set_pull(pin, pull);
586 }
587
588 if (!i) {
589 printf("WARNING: emac: cannot find pins property\n");
590 return -2;
591 }
592
593 return 0;
594 }
595
sun8i_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)596 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
597 {
598 struct emac_eth_dev *priv = dev_get_priv(dev);
599 u32 status, desc_num = priv->rx_currdescnum;
600 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
601 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
602 int length;
603
604 /* Invalidate entire buffer descriptor */
605 cache_inv_descriptor(desc_p);
606
607 status = desc_p->status;
608
609 /* Check for DMA own bit */
610 if (status & EMAC_DESC_OWN_DMA)
611 return -EAGAIN;
612
613 length = (status >> 16) & 0x3fff;
614
615 /* make sure we read from DRAM, not our cache */
616 invalidate_dcache_range(data_start,
617 data_start + roundup(length, ARCH_DMA_MINALIGN));
618
619 if (status & EMAC_DESC_RX_ERROR_MASK) {
620 debug("RX: packet error: 0x%x\n",
621 status & EMAC_DESC_RX_ERROR_MASK);
622 return 0;
623 }
624 if (length < 0x40) {
625 debug("RX: Bad Packet (runt)\n");
626 return 0;
627 }
628
629 if (length > CONFIG_ETH_RXSIZE) {
630 debug("RX: Too large packet (%d bytes)\n", length);
631 return 0;
632 }
633
634 *packetp = (uchar *)(ulong)desc_p->buf_addr;
635
636 return length;
637 }
638
sun8i_emac_eth_send(struct udevice * dev,void * packet,int length)639 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
640 {
641 struct emac_eth_dev *priv = dev_get_priv(dev);
642 u32 desc_num = priv->tx_currdescnum;
643 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
644 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
645 uintptr_t data_end = data_start +
646 roundup(length, ARCH_DMA_MINALIGN);
647
648 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
649
650 memcpy((void *)data_start, packet, length);
651
652 /* Flush data to be sent */
653 flush_dcache_range(data_start, data_end);
654
655 /* frame begin and end */
656 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
657 desc_p->status = EMAC_DESC_OWN_DMA;
658
659 /* make sure the MAC reads the actual data from DRAM */
660 cache_clean_descriptor(desc_p);
661
662 /* Move to next Descriptor and wrap around */
663 if (++desc_num >= CONFIG_TX_DESCR_NUM)
664 desc_num = 0;
665 priv->tx_currdescnum = desc_num;
666
667 /* Start the DMA */
668 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
669
670 /*
671 * Since we copied the data above, we return here without waiting
672 * for the packet to be actually send out.
673 */
674
675 return 0;
676 }
677
sun8i_emac_board_setup(struct udevice * dev,struct emac_eth_dev * priv)678 static int sun8i_emac_board_setup(struct udevice *dev,
679 struct emac_eth_dev *priv)
680 {
681 int ret;
682
683 ret = clk_enable(&priv->tx_clk);
684 if (ret) {
685 dev_err(dev, "failed to enable TX clock\n");
686 return ret;
687 }
688
689 if (reset_valid(&priv->tx_rst)) {
690 ret = reset_deassert(&priv->tx_rst);
691 if (ret) {
692 dev_err(dev, "failed to deassert TX reset\n");
693 goto err_tx_clk;
694 }
695 }
696
697 /* Only H3/H5 have clock controls for internal EPHY */
698 if (clk_valid(&priv->ephy_clk)) {
699 ret = clk_enable(&priv->ephy_clk);
700 if (ret) {
701 dev_err(dev, "failed to enable EPHY TX clock\n");
702 return ret;
703 }
704 }
705
706 if (reset_valid(&priv->ephy_rst)) {
707 ret = reset_deassert(&priv->ephy_rst);
708 if (ret) {
709 dev_err(dev, "failed to deassert EPHY TX clock\n");
710 return ret;
711 }
712 }
713
714 return 0;
715
716 err_tx_clk:
717 clk_disable(&priv->tx_clk);
718 return ret;
719 }
720
721 #if CONFIG_IS_ENABLED(DM_GPIO)
sun8i_mdio_reset(struct mii_dev * bus)722 static int sun8i_mdio_reset(struct mii_dev *bus)
723 {
724 struct udevice *dev = bus->priv;
725 struct emac_eth_dev *priv = dev_get_priv(dev);
726 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
727 int ret;
728
729 if (!dm_gpio_is_valid(&priv->reset_gpio))
730 return 0;
731
732 /* reset the phy */
733 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
734 if (ret)
735 return ret;
736
737 udelay(pdata->reset_delays[0]);
738
739 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
740 if (ret)
741 return ret;
742
743 udelay(pdata->reset_delays[1]);
744
745 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
746 if (ret)
747 return ret;
748
749 udelay(pdata->reset_delays[2]);
750
751 return 0;
752 }
753 #endif
754
sun8i_mdio_init(const char * name,struct udevice * priv)755 static int sun8i_mdio_init(const char *name, struct udevice *priv)
756 {
757 struct mii_dev *bus = mdio_alloc();
758
759 if (!bus) {
760 debug("Failed to allocate MDIO bus\n");
761 return -ENOMEM;
762 }
763
764 bus->read = sun8i_mdio_read;
765 bus->write = sun8i_mdio_write;
766 snprintf(bus->name, sizeof(bus->name), name);
767 bus->priv = (void *)priv;
768 #if CONFIG_IS_ENABLED(DM_GPIO)
769 bus->reset = sun8i_mdio_reset;
770 #endif
771
772 return mdio_register(bus);
773 }
774
sun8i_eth_free_pkt(struct udevice * dev,uchar * packet,int length)775 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
776 int length)
777 {
778 struct emac_eth_dev *priv = dev_get_priv(dev);
779 u32 desc_num = priv->rx_currdescnum;
780 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
781
782 /* give the current descriptor back to the MAC */
783 desc_p->status |= EMAC_DESC_OWN_DMA;
784
785 /* Flush Status field of descriptor */
786 cache_clean_descriptor(desc_p);
787
788 /* Move to next desc and wrap-around condition. */
789 if (++desc_num >= CONFIG_RX_DESCR_NUM)
790 desc_num = 0;
791 priv->rx_currdescnum = desc_num;
792
793 return 0;
794 }
795
sun8i_emac_eth_stop(struct udevice * dev)796 static void sun8i_emac_eth_stop(struct udevice *dev)
797 {
798 struct emac_eth_dev *priv = dev_get_priv(dev);
799
800 /* Stop Rx/Tx transmitter */
801 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
802 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
803
804 /* Stop RX/TX DMA */
805 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
806 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
807
808 phy_shutdown(priv->phydev);
809 }
810
sun8i_emac_eth_probe(struct udevice * dev)811 static int sun8i_emac_eth_probe(struct udevice *dev)
812 {
813 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
814 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
815 struct emac_eth_dev *priv = dev_get_priv(dev);
816 int ret;
817
818 priv->mac_reg = (void *)pdata->iobase;
819
820 ret = sun8i_emac_board_setup(dev, priv);
821 if (ret)
822 return ret;
823
824 sun8i_emac_set_syscon(sun8i_pdata, priv);
825
826 sun8i_mdio_init(dev->name, dev);
827 priv->bus = miiphy_get_dev_by_name(dev->name);
828
829 return sun8i_phy_init(priv, dev);
830 }
831
832 static const struct eth_ops sun8i_emac_eth_ops = {
833 .start = sun8i_emac_eth_start,
834 .write_hwaddr = sun8i_eth_write_hwaddr,
835 .send = sun8i_emac_eth_send,
836 .recv = sun8i_emac_eth_recv,
837 .free_pkt = sun8i_eth_free_pkt,
838 .stop = sun8i_emac_eth_stop,
839 };
840
sun8i_handle_internal_phy(struct udevice * dev,struct emac_eth_dev * priv)841 static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
842 {
843 struct ofnode_phandle_args phandle;
844 int ret;
845
846 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
847 NULL, 0, 0, &phandle);
848 if (ret)
849 return ret;
850
851 /* If the PHY node is not a child of the internal MDIO bus, we are
852 * using some external PHY.
853 */
854 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
855 "allwinner,sun8i-h3-mdio-internal"))
856 return 0;
857
858 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
859 if (ret) {
860 dev_err(dev, "failed to get EPHY TX clock\n");
861 return ret;
862 }
863
864 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
865 if (ret) {
866 dev_err(dev, "failed to get EPHY TX reset\n");
867 return ret;
868 }
869
870 priv->use_internal_phy = true;
871
872 return 0;
873 }
874
sun8i_emac_eth_of_to_plat(struct udevice * dev)875 static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
876 {
877 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
878 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
879 struct emac_eth_dev *priv = dev_get_priv(dev);
880 const char *phy_mode;
881 const fdt32_t *reg;
882 int node = dev_of_offset(dev);
883 int offset = 0;
884 #if CONFIG_IS_ENABLED(DM_GPIO)
885 int reset_flags = GPIOD_IS_OUT;
886 #endif
887 int ret;
888
889 pdata->iobase = dev_read_addr(dev);
890 if (pdata->iobase == FDT_ADDR_T_NONE) {
891 debug("%s: Cannot find MAC base address\n", __func__);
892 return -EINVAL;
893 }
894
895 priv->variant = dev_get_driver_data(dev);
896
897 if (!priv->variant) {
898 printf("%s: Missing variant\n", __func__);
899 return -EINVAL;
900 }
901
902 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
903 if (ret) {
904 dev_err(dev, "failed to get TX clock\n");
905 return ret;
906 }
907
908 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
909 if (ret && ret != -ENOENT) {
910 dev_err(dev, "failed to get TX reset\n");
911 return ret;
912 }
913
914 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
915 if (offset < 0) {
916 debug("%s: cannot find syscon node\n", __func__);
917 return -EINVAL;
918 }
919
920 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
921 if (!reg) {
922 debug("%s: cannot find reg property in syscon node\n",
923 __func__);
924 return -EINVAL;
925 }
926 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
927 offset, reg);
928 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
929 debug("%s: Cannot find syscon base address\n", __func__);
930 return -EINVAL;
931 }
932
933 pdata->phy_interface = -1;
934 priv->phyaddr = -1;
935 priv->use_internal_phy = false;
936
937 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
938 if (offset < 0) {
939 debug("%s: Cannot find PHY address\n", __func__);
940 return -EINVAL;
941 }
942 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
943
944 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
945
946 if (phy_mode)
947 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
948 printf("phy interface%d\n", pdata->phy_interface);
949
950 if (pdata->phy_interface == -1) {
951 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
952 return -EINVAL;
953 }
954
955 if (priv->variant == H3_EMAC) {
956 ret = sun8i_handle_internal_phy(dev, priv);
957 if (ret)
958 return ret;
959 }
960
961 priv->interface = pdata->phy_interface;
962
963 if (!priv->use_internal_phy)
964 parse_phy_pins(dev);
965
966 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
967 "allwinner,tx-delay-ps", 0);
968 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
969 printf("%s: Invalid TX delay value %d\n", __func__,
970 sun8i_pdata->tx_delay_ps);
971
972 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
973 "allwinner,rx-delay-ps", 0);
974 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
975 printf("%s: Invalid RX delay value %d\n", __func__,
976 sun8i_pdata->rx_delay_ps);
977
978 #if CONFIG_IS_ENABLED(DM_GPIO)
979 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
980 "snps,reset-active-low"))
981 reset_flags |= GPIOD_ACTIVE_LOW;
982
983 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
984 &priv->reset_gpio, reset_flags);
985
986 if (ret == 0) {
987 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
988 "snps,reset-delays-us",
989 sun8i_pdata->reset_delays, 3);
990 } else if (ret == -ENOENT) {
991 ret = 0;
992 }
993 #endif
994
995 return 0;
996 }
997
998 static const struct udevice_id sun8i_emac_eth_ids[] = {
999 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1000 {.compatible = "allwinner,sun50i-a64-emac",
1001 .data = (uintptr_t)A64_EMAC },
1002 {.compatible = "allwinner,sun8i-a83t-emac",
1003 .data = (uintptr_t)A83T_EMAC },
1004 {.compatible = "allwinner,sun8i-r40-gmac",
1005 .data = (uintptr_t)R40_GMAC },
1006 {.compatible = "allwinner,sun50i-h6-emac",
1007 .data = (uintptr_t)H6_EMAC },
1008 { }
1009 };
1010
1011 U_BOOT_DRIVER(eth_sun8i_emac) = {
1012 .name = "eth_sun8i_emac",
1013 .id = UCLASS_ETH,
1014 .of_match = sun8i_emac_eth_ids,
1015 .of_to_plat = sun8i_emac_eth_of_to_plat,
1016 .probe = sun8i_emac_eth_probe,
1017 .ops = &sun8i_emac_eth_ops,
1018 .priv_auto = sizeof(struct emac_eth_dev),
1019 .plat_auto = sizeof(struct sun8i_eth_pdata),
1020 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1021 };
1022