1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PCIE3.0 phy driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <generic-phy.h>
12 #include <regmap.h>
13 #include <reset-uclass.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <dm/device_compat.h>
17 #include <dm/lists.h>
18
19 #define GRF_PCIE30PHY_CON1 0x4
20 #define GRF_PCIE30PHY_CON6 0x18
21 #define GRF_PCIE30PHY_CON9 0x24
22
23 /**
24 * struct rockchip_p3phy_priv - RK DW PCIe PHY state
25 *
26 * @mmio: The base address of PHY internal registers
27 * @phy_grf: The regmap for controlling pipe signal
28 * @p30phy: The reset signal for PHY
29 * @ref_clk_m: The reference clock of M for PHY
30 * @ref_clk_n: The reference clock of N for PHY
31 * @pclk: The clock for accessing PHY blocks
32 */
33 struct rockchip_p3phy_priv {
34 void __iomem *mmio;
35 struct regmap *phy_grf;
36 struct reset_ctl p30phy;
37 struct clk ref_clk_m;
38 struct clk ref_clk_n;
39 struct clk pclk;
40 };
41
rochchip_p3phy_init(struct phy * phy)42 static int rochchip_p3phy_init(struct phy *phy)
43 {
44 struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
45 int ret;
46
47 ret = clk_enable(&priv->ref_clk_m);
48 if (ret < 0 && ret != -ENOSYS)
49 return ret;
50
51 ret = clk_enable(&priv->ref_clk_n);
52 if (ret < 0 && ret != -ENOSYS)
53 goto err_ref;
54
55 ret = clk_enable(&priv->pclk);
56 if (ret < 0 && ret != -ENOSYS)
57 goto err_pclk;
58
59 reset_assert(&priv->p30phy);
60 udelay(1);
61
62 /* Deassert PCIe PMA output clamp mode */
63 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
64 (0x1 << 15) | (0x1 << 31));
65
66 reset_deassert(&priv->p30phy);
67 udelay(1);
68
69 return 0;
70 err_pclk:
71 clk_disable(&priv->ref_clk_n);
72 err_ref:
73 clk_disable(&priv->ref_clk_m);
74
75 return ret;
76 }
77
rochchip_p3phy_exit(struct phy * phy)78 static int rochchip_p3phy_exit(struct phy *phy)
79 {
80 struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
81
82 clk_disable(&priv->ref_clk_m);
83 clk_disable(&priv->ref_clk_n);
84 clk_disable(&priv->pclk);
85 reset_assert(&priv->p30phy);
86
87 return 0;
88 }
89
rockchip_p3phy_probe(struct udevice * dev)90 static int rockchip_p3phy_probe(struct udevice *dev)
91 {
92 struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
93 struct udevice *syscon;
94 int ret;
95
96 priv->mmio = (void __iomem *)dev_read_addr(dev);
97 if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
98 return -EINVAL;
99
100 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
101 "rockchip,phy-grf", &syscon);
102 if (ret) {
103 pr_err("unable to find syscon device for rockchip,phy-grf\n");
104 return ret;
105 }
106
107 priv->phy_grf = syscon_get_regmap(syscon);
108 if (IS_ERR(priv->phy_grf)) {
109 dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
110 return PTR_ERR(priv->phy_grf);
111 }
112
113 ret = reset_get_by_name(dev, "phy", &priv->p30phy);
114 if (ret) {
115 dev_err(dev, "no phy reset control specified\n");
116 return ret;
117 }
118
119 ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
120 if (ret) {
121 dev_err(dev, "failed to find ref clock M\n");
122 return PTR_ERR(&priv->ref_clk_m);
123 }
124
125 ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
126 if (ret) {
127 dev_err(dev, "failed to find ref clock N\n");
128 return PTR_ERR(&priv->ref_clk_n);
129 }
130
131 ret = clk_get_by_name(dev, "pclk", &priv->pclk);
132 if (ret) {
133 dev_err(dev, "failed to find pclk\n");
134 return PTR_ERR(&priv->pclk);
135 }
136
137 return 0;
138 }
139
140 static struct phy_ops rochchip_p3phy_ops = {
141 .init = rochchip_p3phy_init,
142 .exit = rochchip_p3phy_exit,
143 };
144
145 static const struct udevice_id rockchip_p3phy_of_match[] = {
146 { .compatible = "rockchip,rk3568-pcie3-phy" },
147 { },
148 };
149
150 U_BOOT_DRIVER(rockchip_pcie3phy) = {
151 .name = "rockchip_pcie3phy",
152 .id = UCLASS_PHY,
153 .of_match = rockchip_p3phy_of_match,
154 .ops = &rochchip_p3phy_ops,
155 .probe = rockchip_p3phy_probe,
156 .priv_auto = sizeof(struct rockchip_p3phy_priv),
157 };
158