1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2018 Xilinx
4 *
5 * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <log.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/cache.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <clk.h>
16 #include <dm.h>
17 #include <malloc.h>
18 #include <memalign.h>
19 #include <spi.h>
20 #include <spi-mem.h>
21 #include <ubi_uboot.h>
22 #include <wait_bit.h>
23 #include <dm/device_compat.h>
24 #include <linux/bitops.h>
25 #include <linux/err.h>
26
27 #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
28 #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
29 #define GQSPI_CONFIG_DMA_MODE (2 << 30)
30 #define GQSPI_CONFIG_CPHA_MASK BIT(2)
31 #define GQSPI_CONFIG_CPOL_MASK BIT(1)
32
33 /*
34 * QSPI Interrupt Registers bit Masks
35 *
36 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
37 * bit definitions.
38 */
39 #define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
40 #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
41 #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
42 #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
43 #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
44 GQSPI_IXR_RXNEMTY_MASK)
45
46 /*
47 * QSPI Enable Register bit Masks
48 *
49 * This register is used to enable or disable the QSPI controller
50 */
51 #define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
52
53 #define GQSPI_GFIFO_LOW_BUS BIT(14)
54 #define GQSPI_GFIFO_CS_LOWER BIT(12)
55 #define GQSPI_GFIFO_UP_BUS BIT(15)
56 #define GQSPI_GFIFO_CS_UPPER BIT(13)
57 #define GQSPI_SPI_MODE_QSPI (3 << 10)
58 #define GQSPI_SPI_MODE_SPI BIT(10)
59 #define GQSPI_SPI_MODE_DUAL_SPI (2 << 10)
60 #define GQSPI_IMD_DATA_CS_ASSERT 5
61 #define GQSPI_IMD_DATA_CS_DEASSERT 5
62 #define GQSPI_GFIFO_TX BIT(16)
63 #define GQSPI_GFIFO_RX BIT(17)
64 #define GQSPI_GFIFO_STRIPE_MASK BIT(18)
65 #define GQSPI_GFIFO_IMD_MASK 0xFF
66 #define GQSPI_GFIFO_EXP_MASK BIT(9)
67 #define GQSPI_GFIFO_DATA_XFR_MASK BIT(8)
68 #define GQSPI_STRT_GEN_FIFO BIT(28)
69 #define GQSPI_GEN_FIFO_STRT_MOD BIT(29)
70 #define GQSPI_GFIFO_WP_HOLD BIT(19)
71 #define GQSPI_BAUD_DIV_MASK (7 << 3)
72 #define GQSPI_DFLT_BAUD_RATE_DIV BIT(3)
73 #define GQSPI_GFIFO_ALL_INT_MASK 0xFBE
74 #define GQSPI_DMA_DST_I_STS_DONE BIT(1)
75 #define GQSPI_DMA_DST_I_STS_MASK 0xFE
76 #define MODEBITS 0x6
77
78 #define GQSPI_GFIFO_SELECT BIT(0)
79 #define GQSPI_FIFO_THRESHOLD 1
80
81 #define SPI_XFER_ON_BOTH 0
82 #define SPI_XFER_ON_LOWER 1
83 #define SPI_XFER_ON_UPPER 2
84
85 #define GQSPI_DMA_ALIGN 0x4
86 #define GQSPI_MAX_BAUD_RATE_VAL 7
87 #define GQSPI_DFLT_BAUD_RATE_VAL 2
88
89 #define GQSPI_TIMEOUT 100000000
90
91 #define GQSPI_BAUD_DIV_SHIFT 2
92 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5
93 #define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2
94 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3
95 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3
96 #define GQSPI_USE_DATA_DLY 0x1
97 #define GQSPI_USE_DATA_DLY_SHIFT 31
98 #define GQSPI_DATA_DLY_ADJ_VALUE 0x2
99 #define GQSPI_DATA_DLY_ADJ_SHIFT 28
100 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
101 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
102 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
103 #define IOU_TAPDLY_BYPASS_OFST 0xFF180390
104 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
105 #define GQSPI_FREQ_40MHZ 40000000
106 #define GQSPI_FREQ_100MHZ 100000000
107 #define GQSPI_FREQ_150MHZ 150000000
108 #define IOU_TAPDLY_BYPASS_MASK 0x7
109
110 #define GQSPI_REG_OFFSET 0x100
111 #define GQSPI_DMA_REG_OFFSET 0x800
112
113 /* QSPI register offsets */
114 struct zynqmp_qspi_regs {
115 u32 confr; /* 0x00 */
116 u32 isr; /* 0x04 */
117 u32 ier; /* 0x08 */
118 u32 idisr; /* 0x0C */
119 u32 imaskr; /* 0x10 */
120 u32 enbr; /* 0x14 */
121 u32 dr; /* 0x18 */
122 u32 txd0r; /* 0x1C */
123 u32 drxr; /* 0x20 */
124 u32 sicr; /* 0x24 */
125 u32 txftr; /* 0x28 */
126 u32 rxftr; /* 0x2C */
127 u32 gpior; /* 0x30 */
128 u32 reserved0; /* 0x34 */
129 u32 lpbkdly; /* 0x38 */
130 u32 reserved1; /* 0x3C */
131 u32 genfifo; /* 0x40 */
132 u32 gqspisel; /* 0x44 */
133 u32 reserved2; /* 0x48 */
134 u32 gqfifoctrl; /* 0x4C */
135 u32 gqfthr; /* 0x50 */
136 u32 gqpollcfg; /* 0x54 */
137 u32 gqpollto; /* 0x58 */
138 u32 gqxfersts; /* 0x5C */
139 u32 gqfifosnap; /* 0x60 */
140 u32 gqrxcpy; /* 0x64 */
141 u32 reserved3[36]; /* 0x68 */
142 u32 gqspidlyadj; /* 0xF8 */
143 };
144
145 struct zynqmp_qspi_dma_regs {
146 u32 dmadst; /* 0x00 */
147 u32 dmasize; /* 0x04 */
148 u32 dmasts; /* 0x08 */
149 u32 dmactrl; /* 0x0C */
150 u32 reserved0; /* 0x10 */
151 u32 dmaisr; /* 0x14 */
152 u32 dmaier; /* 0x18 */
153 u32 dmaidr; /* 0x1C */
154 u32 dmaimr; /* 0x20 */
155 u32 dmactrl2; /* 0x24 */
156 u32 dmadstmsb; /* 0x28 */
157 };
158
159 DECLARE_GLOBAL_DATA_PTR;
160
161 struct zynqmp_qspi_plat {
162 struct zynqmp_qspi_regs *regs;
163 struct zynqmp_qspi_dma_regs *dma_regs;
164 u32 frequency;
165 u32 speed_hz;
166 };
167
168 struct zynqmp_qspi_priv {
169 struct zynqmp_qspi_regs *regs;
170 struct zynqmp_qspi_dma_regs *dma_regs;
171 const void *tx_buf;
172 void *rx_buf;
173 unsigned int len;
174 int bytes_to_transfer;
175 int bytes_to_receive;
176 const struct spi_mem_op *op;
177 };
178
zynqmp_qspi_of_to_plat(struct udevice * bus)179 static int zynqmp_qspi_of_to_plat(struct udevice *bus)
180 {
181 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
182
183 debug("%s\n", __func__);
184
185 plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
186 GQSPI_REG_OFFSET);
187 plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
188 (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
189
190 return 0;
191 }
192
zynqmp_qspi_init_hw(struct zynqmp_qspi_priv * priv)193 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
194 {
195 u32 config_reg;
196 struct zynqmp_qspi_regs *regs = priv->regs;
197
198 writel(GQSPI_GFIFO_SELECT, ®s->gqspisel);
199 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
200 writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
201 writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
202 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
203
204 config_reg = readl(®s->confr);
205 config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
206 GQSPI_CONFIG_MODE_EN_MASK);
207 config_reg |= GQSPI_CONFIG_DMA_MODE |
208 GQSPI_GFIFO_WP_HOLD |
209 GQSPI_DFLT_BAUD_RATE_DIV;
210 writel(config_reg, ®s->confr);
211
212 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
213 }
214
zynqmp_qspi_bus_select(struct zynqmp_qspi_priv * priv)215 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
216 {
217 u32 gqspi_fifo_reg = 0;
218
219 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
220 GQSPI_GFIFO_CS_LOWER;
221
222 return gqspi_fifo_reg;
223 }
224
zynqmp_qspi_genfifo_mode(u8 buswidth)225 static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
226 {
227 switch (buswidth) {
228 case 1:
229 return GQSPI_SPI_MODE_SPI;
230 case 2:
231 return GQSPI_SPI_MODE_DUAL_SPI;
232 case 4:
233 return GQSPI_SPI_MODE_QSPI;
234 default:
235 debug("Unsupported bus width %u\n", buswidth);
236 return GQSPI_SPI_MODE_SPI;
237 }
238 }
239
zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv * priv,u32 gqspi_fifo_reg)240 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
241 u32 gqspi_fifo_reg)
242 {
243 struct zynqmp_qspi_regs *regs = priv->regs;
244 int ret = 0;
245
246 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
247 GQSPI_TIMEOUT, 1);
248 if (ret)
249 printf("%s Timeout\n", __func__);
250
251 writel(gqspi_fifo_reg, ®s->genfifo);
252 }
253
zynqmp_qspi_chipselect(struct zynqmp_qspi_priv * priv,int is_on)254 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
255 {
256 u32 gqspi_fifo_reg = 0;
257
258 if (is_on) {
259 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
260 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
261 GQSPI_IMD_DATA_CS_ASSERT;
262 } else {
263 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
264 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
265 }
266
267 debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
268
269 zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
270 }
271
zynqmp_qspi_set_tapdelay(struct udevice * bus,u32 baudrateval)272 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
273 {
274 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
275 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
276 struct zynqmp_qspi_regs *regs = priv->regs;
277 u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
278 u32 reqhz = 0;
279
280 clk_rate = plat->frequency;
281 reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
282
283 debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
284 __func__, reqhz, clk_rate, baudrateval);
285
286 if (reqhz < GQSPI_FREQ_40MHZ) {
287 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
288 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
289 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
290 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
291 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
292 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
293 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
294 lpbkdlyadj = readl(®s->lpbkdly);
295 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
296 datadlyadj = readl(®s->gqspidlyadj);
297 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
298 | (GQSPI_DATA_DLY_ADJ_VALUE <<
299 GQSPI_DATA_DLY_ADJ_SHIFT));
300 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
301 lpbkdlyadj = readl(®s->lpbkdly);
302 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
303 GQSPI_LPBK_DLY_ADJ_DLY_0);
304 }
305
306 zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
307 tapdlybypass);
308 writel(lpbkdlyadj, ®s->lpbkdly);
309 writel(datadlyadj, ®s->gqspidlyadj);
310 }
311
zynqmp_qspi_set_speed(struct udevice * bus,uint speed)312 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
313 {
314 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
315 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
316 struct zynqmp_qspi_regs *regs = priv->regs;
317 u32 confr;
318 u8 baud_rate_val = 0;
319
320 debug("%s\n", __func__);
321 if (speed > plat->frequency)
322 speed = plat->frequency;
323
324 if (plat->speed_hz != speed) {
325 /* Set the clock frequency */
326 /* If speed == 0, default to lowest speed */
327 while ((baud_rate_val < 8) &&
328 ((plat->frequency /
329 (2 << baud_rate_val)) > speed))
330 baud_rate_val++;
331
332 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
333 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
334
335 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
336
337 confr = readl(®s->confr);
338 confr &= ~GQSPI_BAUD_DIV_MASK;
339 confr |= (baud_rate_val << 3);
340 writel(confr, ®s->confr);
341 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
342
343 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
344 }
345
346 return 0;
347 }
348
zynqmp_qspi_probe(struct udevice * bus)349 static int zynqmp_qspi_probe(struct udevice *bus)
350 {
351 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
352 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
353 struct clk clk;
354 unsigned long clock;
355 int ret;
356
357 debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
358
359 priv->regs = plat->regs;
360 priv->dma_regs = plat->dma_regs;
361
362 ret = clk_get_by_index(bus, 0, &clk);
363 if (ret < 0) {
364 dev_err(bus, "failed to get clock\n");
365 return ret;
366 }
367
368 clock = clk_get_rate(&clk);
369 if (IS_ERR_VALUE(clock)) {
370 dev_err(bus, "failed to get rate\n");
371 return clock;
372 }
373 debug("%s: CLK %ld\n", __func__, clock);
374
375 ret = clk_enable(&clk);
376 if (ret) {
377 dev_err(bus, "failed to enable clock\n");
378 return ret;
379 }
380 plat->frequency = clock;
381 plat->speed_hz = plat->frequency / 2;
382
383 /* init the zynq spi hw */
384 zynqmp_qspi_init_hw(priv);
385
386 return 0;
387 }
388
zynqmp_qspi_set_mode(struct udevice * bus,uint mode)389 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
390 {
391 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
392 struct zynqmp_qspi_regs *regs = priv->regs;
393 u32 confr;
394
395 debug("%s\n", __func__);
396 /* Set the SPI Clock phase and polarities */
397 confr = readl(®s->confr);
398 confr &= ~(GQSPI_CONFIG_CPHA_MASK |
399 GQSPI_CONFIG_CPOL_MASK);
400
401 if (mode & SPI_CPHA)
402 confr |= GQSPI_CONFIG_CPHA_MASK;
403 if (mode & SPI_CPOL)
404 confr |= GQSPI_CONFIG_CPOL_MASK;
405
406 writel(confr, ®s->confr);
407
408 return 0;
409 }
410
zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv * priv,u32 size)411 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
412 {
413 u32 data;
414 int ret = 0;
415 struct zynqmp_qspi_regs *regs = priv->regs;
416 u32 *buf = (u32 *)priv->tx_buf;
417 u32 len = size;
418
419 debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
420 size);
421
422 while (size) {
423 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
424 GQSPI_TIMEOUT, 1);
425 if (ret) {
426 printf("%s: Timeout\n", __func__);
427 return ret;
428 }
429
430 if (size >= 4) {
431 writel(*buf, ®s->txd0r);
432 buf++;
433 size -= 4;
434 } else {
435 switch (size) {
436 case 1:
437 data = *((u8 *)buf);
438 buf += 1;
439 data |= GENMASK(31, 8);
440 break;
441 case 2:
442 data = *((u16 *)buf);
443 buf += 2;
444 data |= GENMASK(31, 16);
445 break;
446 case 3:
447 data = *buf;
448 buf += 3;
449 data |= GENMASK(31, 24);
450 break;
451 }
452 writel(data, ®s->txd0r);
453 size = 0;
454 }
455 }
456
457 priv->tx_buf += len;
458 return 0;
459 }
460
zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv * priv)461 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
462 {
463 const struct spi_mem_op *op = priv->op;
464 u32 gen_fifo_cmd;
465 u8 i, dummy_cycles, addr;
466
467 /* Send opcode */
468 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
469 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
470 gen_fifo_cmd |= GQSPI_GFIFO_TX;
471 gen_fifo_cmd |= op->cmd.opcode;
472 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
473
474 /* Send address */
475 for (i = 0; i < op->addr.nbytes; i++) {
476 addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
477
478 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
479 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
480 gen_fifo_cmd |= GQSPI_GFIFO_TX;
481 gen_fifo_cmd |= addr;
482
483 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
484
485 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
486 }
487
488 /* Send dummy */
489 if (op->dummy.nbytes) {
490 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
491
492 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
493 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
494 gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
495 gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
496 gen_fifo_cmd |= dummy_cycles;
497 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
498 }
499 }
500
zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv * priv,u32 * gen_fifo_cmd)501 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
502 u32 *gen_fifo_cmd)
503 {
504 u32 expval = 8;
505 u32 len;
506
507 while (1) {
508 if (priv->len > 255) {
509 if (priv->len & (1 << expval)) {
510 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
511 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
512 *gen_fifo_cmd |= expval;
513 priv->len -= (1 << expval);
514 return expval;
515 }
516 expval++;
517 } else {
518 *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
519 GQSPI_GFIFO_EXP_MASK);
520 *gen_fifo_cmd |= (u8)priv->len;
521 len = (u8)priv->len;
522 priv->len = 0;
523 return len;
524 }
525 }
526 }
527
zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv * priv)528 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
529 {
530 u32 gen_fifo_cmd;
531 u32 len;
532 int ret = 0;
533
534 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
535 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
536 gen_fifo_cmd |= GQSPI_GFIFO_TX |
537 GQSPI_GFIFO_DATA_XFR_MASK;
538
539 while (priv->len) {
540 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
541 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
542
543 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
544
545 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
546 ret = zynqmp_qspi_fill_tx_fifo(priv,
547 1 << len);
548 else
549 ret = zynqmp_qspi_fill_tx_fifo(priv,
550 len);
551
552 if (ret)
553 return ret;
554 }
555 return ret;
556 }
557
zynqmp_qspi_start_dma(struct zynqmp_qspi_priv * priv,u32 gen_fifo_cmd,u32 * buf)558 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
559 u32 gen_fifo_cmd, u32 *buf)
560 {
561 u32 addr;
562 u32 size, len;
563 u32 actuallen = priv->len;
564 int ret = 0;
565 struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
566
567 writel((unsigned long)buf, &dma_regs->dmadst);
568 writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
569 writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
570 addr = (unsigned long)buf;
571 size = roundup(priv->len, ARCH_DMA_MINALIGN);
572 flush_dcache_range(addr, addr + size);
573
574 while (priv->len) {
575 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
576 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
577 (len % ARCH_DMA_MINALIGN)) {
578 gen_fifo_cmd &= ~GENMASK(7, 0);
579 gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
580 }
581 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
582
583 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
584 }
585
586 ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
587 1, GQSPI_TIMEOUT, 1);
588 if (ret) {
589 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
590 return -ETIMEDOUT;
591 }
592
593 writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
594
595 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
596 (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
597 actuallen);
598
599 if (buf != priv->rx_buf)
600 memcpy(priv->rx_buf, buf, actuallen);
601
602 return 0;
603 }
604
zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv * priv)605 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
606 {
607 u32 gen_fifo_cmd;
608 u32 *buf;
609 u32 actuallen = priv->len;
610
611 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
612 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
613 gen_fifo_cmd |= GQSPI_GFIFO_RX |
614 GQSPI_GFIFO_DATA_XFR_MASK;
615
616 /*
617 * Check if receive buffer is aligned to 4 byte and length
618 * is multiples of four byte as we are using dma to receive.
619 */
620 if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
621 !(actuallen % GQSPI_DMA_ALIGN)) {
622 buf = (u32 *)priv->rx_buf;
623 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
624 }
625
626 ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
627 GQSPI_DMA_ALIGN));
628 buf = (u32 *)tmp;
629 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
630 }
631
zynqmp_qspi_claim_bus(struct udevice * dev)632 static int zynqmp_qspi_claim_bus(struct udevice *dev)
633 {
634 struct udevice *bus = dev->parent;
635 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
636 struct zynqmp_qspi_regs *regs = priv->regs;
637
638 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
639
640 return 0;
641 }
642
zynqmp_qspi_release_bus(struct udevice * dev)643 static int zynqmp_qspi_release_bus(struct udevice *dev)
644 {
645 struct udevice *bus = dev->parent;
646 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
647 struct zynqmp_qspi_regs *regs = priv->regs;
648
649 writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
650
651 return 0;
652 }
653
zynqmp_qspi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)654 static int zynqmp_qspi_exec_op(struct spi_slave *slave,
655 const struct spi_mem_op *op)
656 {
657 struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
658 int ret = 0;
659
660 priv->op = op;
661 priv->tx_buf = op->data.buf.out;
662 priv->rx_buf = op->data.buf.in;
663 priv->len = op->data.nbytes;
664
665 zynqmp_qspi_chipselect(priv, 1);
666
667 /* Send opcode, addr, dummy */
668 zynqmp_qspi_genfifo_cmd(priv);
669
670 /* Request the transfer */
671 if (op->data.dir == SPI_MEM_DATA_IN)
672 ret = zynqmp_qspi_genfifo_fill_rx(priv);
673 else if (op->data.dir == SPI_MEM_DATA_OUT)
674 ret = zynqmp_qspi_genfifo_fill_tx(priv);
675
676 zynqmp_qspi_chipselect(priv, 0);
677
678 return ret;
679 }
680
681 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
682 .exec_op = zynqmp_qspi_exec_op,
683 };
684
685 static const struct dm_spi_ops zynqmp_qspi_ops = {
686 .claim_bus = zynqmp_qspi_claim_bus,
687 .release_bus = zynqmp_qspi_release_bus,
688 .set_speed = zynqmp_qspi_set_speed,
689 .set_mode = zynqmp_qspi_set_mode,
690 .mem_ops = &zynqmp_qspi_mem_ops,
691 };
692
693 static const struct udevice_id zynqmp_qspi_ids[] = {
694 { .compatible = "xlnx,zynqmp-qspi-1.0" },
695 { .compatible = "xlnx,versal-qspi-1.0" },
696 { }
697 };
698
699 U_BOOT_DRIVER(zynqmp_qspi) = {
700 .name = "zynqmp_qspi",
701 .id = UCLASS_SPI,
702 .of_match = zynqmp_qspi_ids,
703 .ops = &zynqmp_qspi_ops,
704 .of_to_plat = zynqmp_qspi_of_to_plat,
705 .plat_auto = sizeof(struct zynqmp_qspi_plat),
706 .priv_auto = sizeof(struct zynqmp_qspi_priv),
707 .probe = zynqmp_qspi_probe,
708 };
709