1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13
14 #include "../gadget/dwc2_udc_otg_priv.h"
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define BIT_WRITEABLE_SHIFT 16
19
20 struct usb2phy_reg {
21 unsigned int offset;
22 unsigned int bitend;
23 unsigned int bitstart;
24 unsigned int disable;
25 unsigned int enable;
26 };
27
28 /**
29 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
30 * @port_reset: usb otg per-port reset register
31 * @soft_con: software control usb otg register
32 * @suspend: phy suspend register
33 */
34 struct rockchip_usb2_phy_cfg {
35 struct usb2phy_reg port_reset;
36 struct usb2phy_reg soft_con;
37 struct usb2phy_reg suspend;
38 };
39
40 struct rockchip_usb2_phy_dt_id {
41 char compatible[128];
42 const void *data;
43 };
44
45 static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
46 .port_reset = {0x00, 12, 12, 0, 1},
47 .soft_con = {0x08, 2, 2, 0, 1},
48 .suspend = {0x0c, 5, 0, 0x01, 0x2A},
49 };
50
51 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
52 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
53 {}
54 };
55
property_enable(struct dwc2_plat_otg_data * pdata,const struct usb2phy_reg * reg,bool en)56 static void property_enable(struct dwc2_plat_otg_data *pdata,
57 const struct usb2phy_reg *reg, bool en)
58 {
59 unsigned int val, mask, tmp;
60
61 tmp = en ? reg->enable : reg->disable;
62 mask = GENMASK(reg->bitend, reg->bitstart);
63 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
64
65 writel(val, pdata->regs_phy + reg->offset);
66 }
67
68
otg_phy_init(struct dwc2_udc * dev)69 void otg_phy_init(struct dwc2_udc *dev)
70 {
71 struct dwc2_plat_otg_data *pdata = dev->pdata;
72 struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
73 struct rockchip_usb2_phy_dt_id *of_id;
74 int i;
75
76 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
77 of_id = &rockchip_usb2_phy_dt_ids[i];
78 if (ofnode_device_is_compatible(pdata->phy_of_node,
79 of_id->compatible)){
80 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
81 break;
82 }
83 }
84 if (!phy_cfg) {
85 debug("Can't find device platform data\n");
86
87 hang();
88 return;
89 }
90 pdata->priv = phy_cfg;
91 /* disable software control */
92 property_enable(pdata, &phy_cfg->soft_con, false);
93
94 /* reset otg port */
95 property_enable(pdata, &phy_cfg->port_reset, true);
96 mdelay(1);
97 property_enable(pdata, &phy_cfg->port_reset, false);
98 udelay(1);
99 }
100
otg_phy_off(struct dwc2_udc * dev)101 void otg_phy_off(struct dwc2_udc *dev)
102 {
103 struct dwc2_plat_otg_data *pdata = dev->pdata;
104 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
105
106 /* enable software control */
107 property_enable(pdata, &phy_cfg->soft_con, true);
108 /* enter suspend */
109 property_enable(pdata, &phy_cfg->suspend, true);
110 }
111