1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
4  */
5 
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <dm/device_compat.h>
10 #include <lcd.h>
11 #include <log.h>
12 #include <panel.h>
13 #include <video.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/utils.h>
17 #include "tilcdc.h"
18 #include "tilcdc-panel.h"
19 
20 #define LCDC_FMAX				200000000
21 
22 /* LCD Control Register */
23 #define LCDC_CTRL_CLK_DIVISOR_MASK		GENMASK(15, 8)
24 #define LCDC_CTRL_RASTER_MODE			BIT(0)
25 #define LCDC_CTRL_CLK_DIVISOR(x)		(((x) & GENMASK(7, 0)) << 8)
26 /* LCD Clock Enable Register */
27 #define LCDC_CLKC_ENABLE_CORECLKEN		BIT(0)
28 #define LCDC_CLKC_ENABLE_LIDDCLKEN		BIT(1)
29 #define LCDC_CLKC_ENABLE_DMACLKEN		BIT(2)
30 /* LCD DMA Control Register */
31 #define LCDC_DMA_CTRL_BURST_SIZE(x)		(((x) & GENMASK(2, 0)) << 4)
32 #define LCDC_DMA_CTRL_BURST_1			0x0
33 #define LCDC_DMA_CTRL_BURST_2			0x1
34 #define LCDC_DMA_CTRL_BURST_4			0x2
35 #define LCDC_DMA_CTRL_BURST_8			0x3
36 #define LCDC_DMA_CTRL_BURST_16			0x4
37 #define LCDC_DMA_CTRL_FIFO_TH(x)		(((x) & GENMASK(2, 0)) << 8)
38 /* LCD Timing_0 Register */
39 #define LCDC_RASTER_TIMING_0_HORMSB(x)	((((x) - 1) & BIT(10)) >> 7)
40 #define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
41 #define LCDC_RASTER_TIMING_0_HSWLSB(x)	((((x) - 1) & GENMASK(5, 0)) << 10)
42 #define LCDC_RASTER_TIMING_0_HFPLSB(x)	((((x) - 1) & GENMASK(7, 0)) << 16)
43 #define LCDC_RASTER_TIMING_0_HBPLSB(x)	((((x) - 1) & GENMASK(7, 0)) << 24)
44 /* LCD Timing_1 Register */
45 #define LCDC_RASTER_TIMING_1_VERLSB(x)		(((x) - 1) & GENMASK(9, 0))
46 #define LCDC_RASTER_TIMING_1_VSW(x)	((((x) - 1) & GENMASK(5, 0)) << 10)
47 #define LCDC_RASTER_TIMING_1_VFP(x)		(((x) & GENMASK(7, 0)) << 16)
48 #define LCDC_RASTER_TIMING_1_VBP(x)		(((x) & GENMASK(7, 0)) << 24)
49 /* LCD Timing_2 Register */
50 #define LCDC_RASTER_TIMING_2_HFPMSB(x)	((((x) - 1) & GENMASK(9, 8)) >> 8)
51 #define LCDC_RASTER_TIMING_2_HBPMSB(x)	((((x) - 1) & GENMASK(9, 8)) >> 4)
52 #define LCDC_RASTER_TIMING_2_ACB(x)		(((x) & GENMASK(7, 0)) << 8)
53 #define LCDC_RASTER_TIMING_2_ACBI(x)		(((x) & GENMASK(3, 0)) << 16)
54 #define LCDC_RASTER_TIMING_2_VSYNC_INVERT	BIT(20)
55 #define LCDC_RASTER_TIMING_2_HSYNC_INVERT	BIT(21)
56 #define LCDC_RASTER_TIMING_2_PXCLK_INVERT	BIT(22)
57 #define LCDC_RASTER_TIMING_2_DE_INVERT		BIT(23)
58 #define LCDC_RASTER_TIMING_2_HSVS_RISEFALL	BIT(24)
59 #define LCDC_RASTER_TIMING_2_HSVS_CONTROL	BIT(25)
60 #define LCDC_RASTER_TIMING_2_VERMSB(x)		((((x) - 1) & BIT(10)) << 16)
61 #define LCDC_RASTER_TIMING_2_HSWMSB(x)	((((x) - 1) & GENMASK(9, 6)) << 21)
62 /* LCD Raster Ctrl Register */
63 #define LCDC_RASTER_CTRL_ENABLE			BIT(0)
64 #define LCDC_RASTER_CTRL_TFT_MODE		BIT(7)
65 #define LCDC_RASTER_CTRL_DATA_ORDER		BIT(8)
66 #define LCDC_RASTER_CTRL_REQDLY(x)		(((x) & GENMASK(7, 0)) << 12)
67 #define LCDC_RASTER_CTRL_PALMODE_RAWDATA	(0x02 << 20)
68 #define LCDC_RASTER_CTRL_TFT_ALT_ENABLE		BIT(23)
69 #define LCDC_RASTER_CTRL_TFT_24BPP_MODE		BIT(25)
70 #define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK	BIT(26)
71 
72 enum {
73 	LCDC_MAX_WIDTH = 2048,
74 	LCDC_MAX_HEIGHT = 2048,
75 	LCDC_MAX_LOG2_BPP = VIDEO_BPP32,
76 };
77 
78 struct tilcdc_regs {
79 	u32 pid;
80 	u32 ctrl;
81 	u32 gap0;
82 	u32 lidd_ctrl;
83 	u32 lidd_cs0_conf;
84 	u32 lidd_cs0_addr;
85 	u32 lidd_cs0_data;
86 	u32 lidd_cs1_conf;
87 	u32 lidd_cs1_addr;
88 	u32 lidd_cs1_data;
89 	u32 raster_ctrl;
90 	u32 raster_timing0;
91 	u32 raster_timing1;
92 	u32 raster_timing2;
93 	u32 raster_subpanel;
94 	u32 raster_subpanel2;
95 	u32 lcddma_ctrl;
96 	u32 lcddma_fb0_base;
97 	u32 lcddma_fb0_ceiling;
98 	u32 lcddma_fb1_base;
99 	u32 lcddma_fb1_ceiling;
100 	u32 sysconfig;
101 	u32 irqstatus_raw;
102 	u32 irqstatus;
103 	u32 irqenable_set;
104 	u32 irqenable_clear;
105 	u32 gap1;
106 	u32 clkc_enable;
107 	u32 clkc_reset;
108 };
109 
110 struct tilcdc_priv {
111 	struct tilcdc_regs *regs;
112 	struct clk gclk;
113 	struct clk dpll_m2_clk;
114 };
115 
116 DECLARE_GLOBAL_DATA_PTR;
117 
tilcdc_set_pixel_clk_rate(struct udevice * dev,ulong rate)118 static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate)
119 {
120 	struct tilcdc_priv *priv = dev_get_priv(dev);
121 	struct tilcdc_regs *regs = priv->regs;
122 	ulong mult_rate, mult_round_rate, best_err, err;
123 	u32 v;
124 	int div, i;
125 
126 	best_err = rate;
127 	div = 0;
128 	for (i = 2; i <= 255; i++) {
129 		mult_rate = rate * i;
130 		mult_round_rate = clk_round_rate(&priv->gclk, mult_rate);
131 		if (IS_ERR_VALUE(mult_round_rate))
132 			return mult_round_rate;
133 
134 		err = mult_rate - mult_round_rate;
135 		if (err < best_err) {
136 			best_err = err;
137 			div = i;
138 			if (err == 0)
139 				break;
140 		}
141 	}
142 
143 	if (div == 0) {
144 		dev_err(dev, "failed to find a divisor\n");
145 		return -EFAULT;
146 	}
147 
148 	mult_rate = clk_set_rate(&priv->gclk, rate * div);
149 	v = readl(&regs->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
150 	v |= LCDC_CTRL_CLK_DIVISOR(div);
151 	writel(v, &regs->ctrl);
152 	rate = mult_rate / div;
153 	dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err);
154 	return rate;
155 }
156 
tilcdc_remove(struct udevice * dev)157 static int tilcdc_remove(struct udevice *dev)
158 {
159 	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
160 	struct tilcdc_priv *priv = dev_get_priv(dev);
161 
162 	uc_plat->base -= 0x20;
163 	uc_plat->size += 0x20;
164 	clk_release_all(&priv->gclk, 1);
165 	clk_release_all(&priv->dpll_m2_clk, 1);
166 	return 0;
167 }
168 
tilcdc_probe(struct udevice * dev)169 static int tilcdc_probe(struct udevice *dev)
170 {
171 	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
172 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
173 	struct tilcdc_priv *priv = dev_get_priv(dev);
174 	struct tilcdc_regs *regs = priv->regs;
175 	struct udevice *panel, *clk_dev;
176 	struct tilcdc_panel_info info;
177 	struct display_timing timing;
178 	ulong rate;
179 	u32 reg;
180 	int err;
181 
182 	/* Before relocation we don't need to do anything */
183 	if (!(gd->flags & GD_FLG_RELOC))
184 		return 0;
185 
186 	err = uclass_get_device(UCLASS_PANEL, 0, &panel);
187 	if (err) {
188 		dev_err(dev, "failed to get panel\n");
189 		return err;
190 	}
191 
192 	err = panel_get_display_timing(panel, &timing);
193 	if (err) {
194 		dev_err(dev, "failed to get display timing\n");
195 		return err;
196 	}
197 
198 	if (timing.pixelclock.typ > (LCDC_FMAX / 2)) {
199 		dev_err(dev, "invalid display clock-frequency: %d Hz\n",
200 			timing.pixelclock.typ);
201 		return -EINVAL;
202 	}
203 
204 	if (timing.hactive.typ > LCDC_MAX_WIDTH)
205 		timing.hactive.typ = LCDC_MAX_WIDTH;
206 
207 	if (timing.vactive.typ > LCDC_MAX_HEIGHT)
208 		timing.vactive.typ = LCDC_MAX_HEIGHT;
209 
210 	err = tilcdc_panel_get_display_info(panel, &info);
211 	if (err) {
212 		dev_err(dev, "failed to get panel info\n");
213 		return err;
214 	}
215 
216 	switch (info.bpp) {
217 	case 16:
218 	case 24:
219 	case 32:
220 		break;
221 	default:
222 		dev_err(dev, "invalid seting, bpp: %d\n", info.bpp);
223 		return -EINVAL;
224 	}
225 
226 	switch (info.dma_burst_sz) {
227 	case 1:
228 	case 2:
229 	case 4:
230 	case 8:
231 	case 16:
232 		break;
233 	default:
234 		dev_err(dev, "invalid setting, dma-burst-sz: %d\n",
235 			info.dma_burst_sz);
236 		return -EINVAL;
237 	}
238 
239 	err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
240 	if (err) {
241 		dev_err(dev, "failed to get lcd_gclk device\n");
242 		return err;
243 	}
244 
245 	err = clk_request(clk_dev, &priv->gclk);
246 	if (err) {
247 		dev_err(dev, "failed to get %s clock\n", clk_dev->name);
248 		return err;
249 	}
250 
251 	rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ);
252 	if (IS_ERR_VALUE(rate)) {
253 		dev_err(dev, "failed to set pixel clock rate\n");
254 		return rate;
255 	}
256 
257 	err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
258 					&clk_dev);
259 	if (err) {
260 		dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
261 		return err;
262 	}
263 
264 	err = clk_request(clk_dev, &priv->dpll_m2_clk);
265 	if (err) {
266 		dev_err(dev, "failed to get %s clock\n", clk_dev->name);
267 		return err;
268 	}
269 
270 	err = clk_set_parent(&priv->gclk, &priv->dpll_m2_clk);
271 	if (err) {
272 		dev_err(dev, "failed to set %s clock as %s's parent\n",
273 			priv->dpll_m2_clk.dev->name, priv->gclk.dev->name);
274 		return err;
275 	}
276 
277 	/* palette default entry */
278 	memset((void *)uc_plat->base, 0, 0x20);
279 	*(unsigned int *)uc_plat->base = 0x4000;
280 	/* point fb behind palette */
281 	uc_plat->base += 0x20;
282 	uc_plat->size -= 0x20;
283 
284 	writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN |
285 	       LCDC_CLKC_ENABLE_DMACLKEN, &regs->clkc_enable);
286 	writel(0, &regs->raster_ctrl);
287 
288 	reg = readl(&regs->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK;
289 	reg |= LCDC_CTRL_RASTER_MODE;
290 	writel(reg, &regs->ctrl);
291 
292 	reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3;
293 	reg += uc_plat->base;
294 	writel(uc_plat->base, &regs->lcddma_fb0_base);
295 	writel(reg, &regs->lcddma_fb0_ceiling);
296 	writel(uc_plat->base, &regs->lcddma_fb1_base);
297 	writel(reg, &regs->lcddma_fb1_ceiling);
298 
299 	reg = LCDC_DMA_CTRL_FIFO_TH(info.fifo_th);
300 	switch (info.dma_burst_sz) {
301 	case 1:
302 		reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1);
303 		break;
304 	case 2:
305 		reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2);
306 		break;
307 	case 4:
308 		reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4);
309 		break;
310 	case 8:
311 		reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8);
312 		break;
313 	case 16:
314 		reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
315 		break;
316 	}
317 
318 	writel(reg, &regs->lcddma_ctrl);
319 
320 	writel(LCDC_RASTER_TIMING_0_HORLSB(timing.hactive.typ) |
321 	       LCDC_RASTER_TIMING_0_HORMSB(timing.hactive.typ) |
322 	       LCDC_RASTER_TIMING_0_HFPLSB(timing.hfront_porch.typ) |
323 	       LCDC_RASTER_TIMING_0_HBPLSB(timing.hback_porch.typ) |
324 	       LCDC_RASTER_TIMING_0_HSWLSB(timing.hsync_len.typ),
325 	       &regs->raster_timing0);
326 
327 	writel(LCDC_RASTER_TIMING_1_VBP(timing.vback_porch.typ) |
328 	       LCDC_RASTER_TIMING_1_VFP(timing.vfront_porch.typ) |
329 	       LCDC_RASTER_TIMING_1_VSW(timing.vsync_len.typ) |
330 	       LCDC_RASTER_TIMING_1_VERLSB(timing.vactive.typ),
331 	       &regs->raster_timing1);
332 
333 	reg = LCDC_RASTER_TIMING_2_ACB(info.ac_bias) |
334 		LCDC_RASTER_TIMING_2_ACBI(info.ac_bias_intrpt) |
335 		LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) |
336 		LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) |
337 		LCDC_RASTER_TIMING_2_HBPMSB(timing.hback_porch.typ) |
338 		LCDC_RASTER_TIMING_2_HFPMSB(timing.hfront_porch.typ);
339 
340 	if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
341 		reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT;
342 
343 	if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
344 		reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT;
345 
346 	if (info.invert_pxl_clk)
347 		reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT;
348 
349 	if (info.sync_edge)
350 		reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL;
351 
352 	if (info.sync_ctrl)
353 		reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL;
354 
355 	writel(reg, &regs->raster_timing2);
356 
357 	reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE |
358 		LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(info.fdd);
359 
360 	if (info.tft_alt_mode)
361 		reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE;
362 
363 	if (info.bpp == 24)
364 		reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
365 	else if (info.bpp == 32)
366 		reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE |
367 			LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
368 
369 	if (info.raster_order)
370 		reg |= LCDC_RASTER_CTRL_DATA_ORDER;
371 
372 	writel(reg, &regs->raster_ctrl);
373 
374 	uc_priv->xsize = timing.hactive.typ;
375 	uc_priv->ysize = timing.vactive.typ;
376 	uc_priv->bpix = log_2_n_round_up(info.bpp);
377 
378 	err = panel_enable_backlight(panel);
379 	if (err) {
380 		dev_err(dev, "failed to enable panel backlight\n");
381 		return err;
382 	}
383 
384 	return 0;
385 }
386 
tilcdc_of_to_plat(struct udevice * dev)387 static int tilcdc_of_to_plat(struct udevice *dev)
388 {
389 	struct tilcdc_priv *priv = dev_get_priv(dev);
390 
391 	priv->regs = (struct tilcdc_regs *)dev_read_addr(dev);
392 	if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
393 		dev_err(dev, "failed to get base address\n");
394 		return -EINVAL;
395 	}
396 
397 	dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs);
398 	return 0;
399 }
400 
tilcdc_bind(struct udevice * dev)401 static int tilcdc_bind(struct udevice *dev)
402 {
403 	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
404 
405 	uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT *
406 			  (1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20;
407 
408 	dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size);
409 	return 0;
410 }
411 
412 static const struct udevice_id tilcdc_ids[] = {
413 	{.compatible = "ti,am33xx-tilcdc"},
414 	{}
415 };
416 
417 U_BOOT_DRIVER(tilcdc) = {
418 	.name = "tilcdc",
419 	.id = UCLASS_VIDEO,
420 	.of_match = tilcdc_ids,
421 	.bind = tilcdc_bind,
422 	.of_to_plat = tilcdc_of_to_plat,
423 	.probe = tilcdc_probe,
424 	.remove = tilcdc_remove,
425 	.priv_auto = sizeof(struct tilcdc_priv)
426 };
427