1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <wdt.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <linux/bitfield.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define CORE0_WDOG_OFFSET 0x40000
19 #define CORE0_POKE_OFFSET 0x50000
20 #define CORE0_POKE_OFFSET_MASK 0xfffffULL
21
22 #define WDOG_MODE GENMASK_ULL(1, 0)
23 #define WDOG_LEN GENMASK_ULL(19, 4)
24 #define WDOG_CNT GENMASK_ULL(43, 20)
25
26 struct octeontx_wdt {
27 void __iomem *reg;
28 struct clk clk;
29 };
30
octeontx_wdt_start(struct udevice * dev,u64 timeout_ms,ulong flags)31 static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
32 {
33 struct octeontx_wdt *priv = dev_get_priv(dev);
34 u64 clk_rate, val;
35 u64 tout_wdog;
36
37 clk_rate = clk_get_rate(&priv->clk);
38 if (IS_ERR_VALUE(clk_rate))
39 return -EINVAL;
40
41 /* Watchdog counts in 1024 cycle steps */
42 tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
43
44 /*
45 * We can only specify the upper 16 bits of a 24 bit value.
46 * Round up
47 */
48 tout_wdog = (tout_wdog + 0xff) >> 8;
49
50 /* If the timeout overflows the hardware limit, set max */
51 if (tout_wdog >= 0x10000)
52 tout_wdog = 0xffff;
53
54 val = FIELD_PREP(WDOG_MODE, 0x3) |
55 FIELD_PREP(WDOG_LEN, tout_wdog) |
56 FIELD_PREP(WDOG_CNT, tout_wdog << 8);
57 writeq(val, priv->reg + CORE0_WDOG_OFFSET);
58
59 return 0;
60 }
61
octeontx_wdt_stop(struct udevice * dev)62 static int octeontx_wdt_stop(struct udevice *dev)
63 {
64 struct octeontx_wdt *priv = dev_get_priv(dev);
65
66 writeq(0, priv->reg + CORE0_WDOG_OFFSET);
67
68 return 0;
69 }
70
octeontx_wdt_expire_now(struct udevice * dev,ulong flags)71 static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
72 {
73 octeontx_wdt_stop(dev);
74
75 /* Start with 100ms timeout to expire immediately */
76 octeontx_wdt_start(dev, 100, flags);
77
78 return 0;
79 }
80
octeontx_wdt_reset(struct udevice * dev)81 static int octeontx_wdt_reset(struct udevice *dev)
82 {
83 struct octeontx_wdt *priv = dev_get_priv(dev);
84
85 writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
86
87 return 0;
88 }
89
octeontx_wdt_remove(struct udevice * dev)90 static int octeontx_wdt_remove(struct udevice *dev)
91 {
92 octeontx_wdt_stop(dev);
93
94 return 0;
95 }
96
octeontx_wdt_probe(struct udevice * dev)97 static int octeontx_wdt_probe(struct udevice *dev)
98 {
99 struct octeontx_wdt *priv = dev_get_priv(dev);
100 int ret;
101
102 priv->reg = dev_remap_addr(dev);
103 if (!priv->reg)
104 return -EINVAL;
105
106 /*
107 * Save base register address in reg masking lower 20 bits
108 * as 0xa0000 appears when extracted from the DT
109 */
110 priv->reg = (void __iomem *)(((u64)priv->reg &
111 ~CORE0_POKE_OFFSET_MASK));
112
113 ret = clk_get_by_index(dev, 0, &priv->clk);
114 if (ret < 0)
115 return ret;
116
117 ret = clk_enable(&priv->clk);
118 if (ret)
119 return ret;
120
121 return 0;
122 }
123
124 static const struct wdt_ops octeontx_wdt_ops = {
125 .reset = octeontx_wdt_reset,
126 .start = octeontx_wdt_start,
127 .stop = octeontx_wdt_stop,
128 .expire_now = octeontx_wdt_expire_now,
129 };
130
131 static const struct udevice_id octeontx_wdt_ids[] = {
132 { .compatible = "arm,sbsa-gwdt" },
133 {}
134 };
135
136 U_BOOT_DRIVER(wdt_octeontx) = {
137 .name = "wdt_octeontx",
138 .id = UCLASS_WDT,
139 .of_match = octeontx_wdt_ids,
140 .ops = &octeontx_wdt_ops,
141 .priv_auto = sizeof(struct octeontx_wdt),
142 .probe = octeontx_wdt_probe,
143 .remove = octeontx_wdt_remove,
144 .flags = DM_FLAG_OS_PREPARE,
145 };
146