1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4  */
5 
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
8 
9 /*
10  * High Level Configuration Options (easy to change)
11  */
12 
13 /*
14  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15  * for DDR ECC byte filling in the SPL before loading the main
16  * U-Boot into it.
17  */
18 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
19 
20 /* I2C */
21 #define CONFIG_SYS_I2C
22 #define CONFIG_SYS_I2C_MVTWSI
23 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
24 #define CONFIG_SYS_I2C_SLAVE		0x0
25 #define CONFIG_SYS_I2C_SPEED		100000
26 
27 /* SPI NOR flash default params, used by sf commands */
28 
29 /* Environment in SPI NOR flash */
30 
31 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
32 
33 /*
34  * mv-common.h should be defined after CMD configs since it used them
35  * to enable certain macros
36  */
37 #include "mv-common.h"
38 
39 /*
40  * Memory layout while starting into the bin_hdr via the
41  * BootROM:
42  *
43  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
44  * 0x4000.4030			bin_hdr start address
45  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
46  * 0x4007.fffc			BootROM stack top
47  *
48  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
49  * L2 cache thus cannot be used.
50  */
51 
52 /* SPL */
53 /* Defines for SPL */
54 #define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
55 
56 #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
57 #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
58 
59 #ifdef CONFIG_SPL_BUILD
60 #define CONFIG_SYS_MALLOC_SIMPLE
61 #endif
62 
63 #define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
64 #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
65 
66 /* SPL related SPI defines */
67 
68 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
69 #define CONFIG_DDR_FIXED_SIZE		(1 << 20)	/* 1GiB */
70 #define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
71 
72 #endif /* _CONFIG_DB_MV7846MP_GP_H */
73