1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8 #ifndef __CONFIG_MT7628_H 9 #define __CONFIG_MT7628_H 10 11 #define CONFIG_SYS_HZ 1000 12 #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 13 14 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 15 16 #define CONFIG_SYS_MALLOC_LEN 0x100000 17 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 18 19 #define CONFIG_SYS_SDRAM_BASE 0x80000000 20 #define CONFIG_SYS_LOAD_ADDR 0x80010000 21 22 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 23 24 #define CONFIG_SYS_BOOTM_LEN 0x1000000 25 26 #define CONFIG_SYS_MAXARGS 16 27 #define CONFIG_SYS_CBSIZE 1024 28 29 /* Serial SPL */ 30 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) 31 #define CONFIG_SYS_NS16550_MEM32 32 #define CONFIG_SYS_NS16550_CLK 40000000 33 #define CONFIG_SYS_NS16550_REG_SIZE -4 34 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 35 #endif 36 37 /* Serial common */ 38 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 39 230400, 460800, 921600 } 40 41 /* SPL */ 42 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 #endif 45 46 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SPL_BSS_START_ADDR 0x80010000 48 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 49 #define CONFIG_SPL_MAX_SIZE 0x10000 50 #define CONFIG_SPL_PAD_TO 0 51 52 /* Dummy value */ 53 #define CONFIG_SYS_UBOOT_BASE 0 54 55 #endif /* __CONFIG_MT7628_H */ 56