The PMSFCR_EL1 characteristics are:
Controls sample filtering. The filter is the logical AND of the FL, FT and FE bits. For example, if FE == 1 and FT == 1 only samples including the selected operation types and the selected events will be recorded
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSFCR_EL1 are UNDEFINED.
PMSFCR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | ST | LD | B | RES0 | FDS | FnE | FL | FT | FE | ||||||||||||||||||||||
Reserved, RES0.
Store filter enable.
| ST | Meaning |
|---|---|
| 0b0 |
Do not record store operations. |
| 0b1 |
Record all store operations |
This field is ignored by the PE when PMSFCR_EL1.FT == 0.
For filtering purposes, store operations include vector stores and all atomic operations.
The reset behavior of this field is:
Load filter enable.
| LD | Meaning |
|---|---|
| 0b0 |
Do not record load operations. |
| 0b1 |
Record all load operations |
This field is ignored by the PE when PMSFCR_EL1.FT == 0.
For filtering purposes, load operations include vector loads and atomic operations that return a value to the PE.
The reset behavior of this field is:
Branch filter enable.
| B | Meaning |
|---|---|
| 0b0 |
Do not record branch operations. |
| 0b1 |
Record all branch operations |
This field is ignored by the PE when PMSFCR_EL1.FT == 0.
For filtering purposes, branch operations include exception returns.
The reset behavior of this field is:
Reserved, RES0.
Filter by Data Source.
| FDS | Meaning |
|---|---|
| 0b0 |
Data Source filtering disabled. |
| 0b1 |
Data Source filtering enabled. Samples of load instructions reporting a Data Source not selected by PMSDSFR_EL1 will not be recorded. |
If PMSFCR_EL1.FDS == 1 and PMSDSFR_EL1 is zero, then no load operations with a Data Source will be recorded.
Load operations without a Data Source and other sampled operations are unaffected by this field.
The reset behavior of this field is:
Reserved, RES0.
Filter by event, inverted.
| FnE | Meaning |
|---|---|
| 0b0 |
Inverted event filtering disabled. |
| 0b1 |
Inverted event filtering enabled. Samples including the events selected by PMSNEVFR_EL1 will not be recorded. |
If any of the following are true, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FnE == 0:
The reset behavior of this field is:
Reserved, RES0.
Filter by latency
| FL | Meaning |
|---|---|
| 0b0 |
Latency filtering disabled |
| 0b1 |
Latency filtering enabled. Samples with a total latency less than PMSLATFR_EL1.MINLAT will not be recorded |
If this field is set to 1 and PMSLATFR_EL1.MINLAT is set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FL is set to 0
The reset behavior of this field is:
Filter by operation type. The filter is the logical OR of the ST, LD and B bits. For example, if LD and ST are both set, both load and store operations are recorded
| FT | Meaning |
|---|---|
| 0b0 |
Type filtering disabled |
| 0b1 |
Type filtering enabled. Samples not one of the selected operation types will not be recorded |
If this field is set to 1 and the PMSFCR_EL1.{ST, LD, B} bits are all set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FT is set to 0
The reset behavior of this field is:
Filter by event.
| FE | Meaning |
|---|---|
| 0b0 |
Event filtering disabled. |
| 0b1 |
Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1 will not be recorded. |
If any of the following are true, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FE == 0:
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSFCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSFCR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSFCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSFCR_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMSFCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSFCR_EL1 = X[t, 64];
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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