PMSNEVFR

Controls sample filtering by events. The overall inverted filter is the logical OR of these filters. For example, if PMSNEVFR_EL1.E[3] and PMSNEVFR_EL1.E[5] are both set to 1, samples that have either event 3 (Level 1 unified or data cache refill) or event 5 (TLB walk) set to 1 are not recorded.

Configuration

This register is present only when FEAT_SPEv1p2 is implemented. Otherwise, direct accesses to PMSNEVFR_EL1 are UNDEFINED.

Attributes

Field descriptions

E[<x>], bit [x], for x = 63 to 48, 31 to 24, 15 to 12

E[<x>] is the event filter for IMPLEMENTATION DEFINED event <x>.

E[<x>]	Meaning
0b0	Event <x> is ignored.
0b1	Do not record samples that have event <x> == 1.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSNEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This bit is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When event <x> is not implemented, or filtering on event <x> is not supported, access to this field is RAZ/WI.

Bits [47:32]

E[23], bit [23]
When FEAT_SPEv1p4 is implemented and event 23 is implemented:

E[23]	Meaning
0b0	Data snooped event is ignored.
0b1	Do not record samples that have the Data snooped event == 1.

Otherwise:

E[22], bit [22]
When FEAT_SPEv1p4 is implemented and event 22 is implemented:

E[22]	Meaning
0b0	Recently fetched event is ignored.
0b1	Do not record samples that have the Recently fetched event == 1.

Otherwise:

E[21], bit [21]
When FEAT_SPEv1p4 is implemented and event 21 is implemented:

E[21]	Meaning
0b0	Cache data modified event is ignored.
0b1	Do not record samples that have the Cache data modified event == 1.

Otherwise:

E[20], bit [20]
When FEAT_SPEv1p4 is implemented and event 20 is implemented:

E[20]	Meaning
0b0	Level 2 data cache miss event is ignored.
0b1	Do not record samples that have the Level 2 data cache miss event == 1.

Otherwise:

E[19], bit [19]
When FEAT_SPEv1p4 is implemented and event 19 is implemented:

E[19]	Meaning
0b0	Level 2 data cache access event is ignored.
0b1	Do not record samples that have the Level 2 data cache access event == 1.

Otherwise:

E[18], bit [18]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

E[18]	Meaning
0b0	Empty predicate event is ignored.
0b1	Do not record samples that have the Empty predicate event == 1.

Otherwise:

E[17], bit [17]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

E[17]	Meaning
0b0	Partial predicate event is ignored.
0b1	Do not record samples that have the Partial predicate event == 1.

Otherwise:

E[16], bit [16]
When FEAT_TME is implemented:

E[16]	Meaning
0b0	Transactional event is ignored.
0b1	Do not record samples that have the Transactional event == 1.

Otherwise:

E[11], bit [11]
When FEAT_SPEv1p1 is implemented:

E[11]	Meaning
0b0	Misalignment event is ignored.
0b1	Do not record samples that have the Misalignment event == 1.

Otherwise:

E[10], bit [10]
When (FEAT_SPEv1p4 is implemented or filtering on event 10 is optionally supported) and event 10 is implemented:

E[10]	Meaning
0b0	Remote access event is ignored.
0b1	Do not record samples that have the Remote access event == 1.

Otherwise:

E[9], bit [9]
When (FEAT_SPEv1p4 is implemented or filtering on event 9 is optionally supported) and event 9 is implemented:

E[9]	Meaning
0b0	Last Level cache miss event is ignored.
0b1	Do not record samples that have the Last Level cache miss event == 1.

Otherwise:

E[8], bit [8]
When (FEAT_SPEv1p4 is implemented or filtering on event 8 is optionally supported) and event 8 is implemented:

E[8]	Meaning
0b0	Last Level cache access event is ignored.
0b1	Do not record samples that have the Last Level cache access event == 1.

Otherwise:

E[7], bit [7]

E[6], bit [6]

E[5], bit [5]

E[7]	Meaning
0b0	Mispredicted event is ignored.
0b1	Do not record samples that have the Mispredicted event == 1.

E[6]	Meaning
0b0	Not taken event is ignored.
0b1	Do not record samples that have the Not taken event == 1.

E[5]	Meaning
0b0	TLB walk event is ignored.
0b1	Do not record samples that have the TLB walk event == 1.

E[4], bit [4]
When FEAT_SPEv1p4 is implemented or filtering on event 4 is optionally supported:

E[4]	Meaning
0b0	TLB access event is ignored.
0b1	Do not record samples that have the TLB access event == 1.

Otherwise:

E[3], bit [3]

E[3]	Meaning
0b0	Level 1 data or unified cache refill event is ignored.
0b1	Do not record samples that have the Level 1 data or unified cache refill event == 1.

E[2], bit [2]
When FEAT_SPEv1p4 is implemented or filtering on event 2 is optionally supported:

E[2]	Meaning
0b0	Level 1 data cache access event is ignored.
0b1	Do not record samples that have the Level 1 data cache access event == 1.

Otherwise:

E[1], bit [1]
When the PE supports sampling of speculative instructions:

E[1]	Meaning
0b0	Architecturally executed event is ignored.
0b1	Do not record samples that have the Architecturally executed event == 1.

Otherwise:

Bit [0]

Accessing PMSNEVFR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSNEVFR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.nPMSNEVFR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then X[t, 64] = NVMem[0x850]; else X[t, 64] = PMSNEVFR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSNEVFR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSNEVFR_EL1;

MSR PMSNEVFR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.nPMSNEVFR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x850] = X[t, 64]; else PMSNEVFR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSNEVFR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSNEVFR_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
E[63]	E[62]	E[61]	E[60]	E[59]	E[58]	E[57]	E[56]	E[55]	E[54]	E[53]	E[52]	E[51]	E[50]	E[49]	E[48]	RAZ/WI
E[31]	E[30]	E[29]	E[28]	E[27]	E[26]	E[25]	E[24]	E[23]	E[22]	E[21]	E[20]	E[19]	E[18]	E[17]	E[16]	E[15]	E[14]	E[13]	E[12]	E[11]	E[10]	E[9]	E[8]	E[7]	E[6]	E[5]	E[4]	E[3]	E[2]	E[1]	RAZ/WI

PMSNEVFR_EL1, Sampling Inverted Event Filter Register

Purpose

Configuration

Attributes

Field descriptions

E[<x>], bit [x], for x = 63 to 48, 31 to 24, 15 to 12

Bits [47:32]

E[23], bit [23]When FEAT_SPEv1p4 is implemented and event 23 is implemented:

Otherwise:

E[22], bit [22]When FEAT_SPEv1p4 is implemented and event 22 is implemented:

Otherwise:

E[21], bit [21]When FEAT_SPEv1p4 is implemented and event 21 is implemented:

Otherwise:

E[20], bit [20]When FEAT_SPEv1p4 is implemented and event 20 is implemented:

Otherwise:

E[19], bit [19]When FEAT_SPEv1p4 is implemented and event 19 is implemented:

Otherwise:

E[18], bit [18]When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

Otherwise:

E[17], bit [17]When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

Otherwise:

E[16], bit [16]When FEAT_TME is implemented:

Otherwise:

E[11], bit [11]When FEAT_SPEv1p1 is implemented:

Otherwise:

E[10], bit [10]When (FEAT_SPEv1p4 is implemented or filtering on event 10 is optionally supported) and event 10 is implemented:

Otherwise:

E[9], bit [9]When (FEAT_SPEv1p4 is implemented or filtering on event 9 is optionally supported) and event 9 is implemented:

Otherwise:

E[8], bit [8]When (FEAT_SPEv1p4 is implemented or filtering on event 8 is optionally supported) and event 8 is implemented:

Otherwise:

E[7], bit [7]

E[6], bit [6]

E[5], bit [5]

E[4], bit [4]When FEAT_SPEv1p4 is implemented or filtering on event 4 is optionally supported:

Otherwise:

E[3], bit [3]

E[2], bit [2]When FEAT_SPEv1p4 is implemented or filtering on event 2 is optionally supported:

Otherwise:

E[1], bit [1]When the PE supports sampling of speculative instructions:

Otherwise:

Bit [0]

Accessing PMSNEVFR_EL1

MRS <Xt>, PMSNEVFR_EL1

MSR PMSNEVFR_EL1, <Xt>

E[23], bit [23]
When FEAT_SPEv1p4 is implemented and event 23 is implemented:

E[22], bit [22]
When FEAT_SPEv1p4 is implemented and event 22 is implemented:

E[21], bit [21]
When FEAT_SPEv1p4 is implemented and event 21 is implemented:

E[20], bit [20]
When FEAT_SPEv1p4 is implemented and event 20 is implemented:

E[19], bit [19]
When FEAT_SPEv1p4 is implemented and event 19 is implemented:

E[18], bit [18]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

E[17], bit [17]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

E[16], bit [16]
When FEAT_TME is implemented:

E[11], bit [11]
When FEAT_SPEv1p1 is implemented:

E[10], bit [10]
When (FEAT_SPEv1p4 is implemented or filtering on event 10 is optionally supported) and event 10 is implemented:

E[9], bit [9]
When (FEAT_SPEv1p4 is implemented or filtering on event 9 is optionally supported) and event 9 is implemented:

E[8], bit [8]
When (FEAT_SPEv1p4 is implemented or filtering on event 8 is optionally supported) and event 8 is implemented:

E[4], bit [4]
When FEAT_SPEv1p4 is implemented or filtering on event 4 is optionally supported:

E[2], bit [2]
When FEAT_SPEv1p4 is implemented or filtering on event 2 is optionally supported:

E[1], bit [1]
When the PE supports sampling of speculative instructions: